The blanket silicon etch process performed on the SPTS Rapier XE achieves an etch rate >8.5µm/min, high selectivity (Si:SiO>150:1), and is ~3-4x faster than competing systems. A unique dual plasma source design creates a uniform etch (<±3%) across a 300mm wafer, which can be “tuned” to compensate for variations in in-coming wafer thicknesses.
Testimonial
Via reveal is a 2.5D/3D technology, where the back of the wafer is etched to reveal the tips of the Cu filled vias, ready for bumping. Launched in May 2014, the Rapier XE has been developed to improve etch rates and uniformities for blanket silicon etches on 300mm wafers. The Rapier XE will lower costs and increase yields for device manufacturers utilizing through-silicon vias (TSVs).
Higher etch rates benefit throughput and CoO. Improved uniformity and selectivity increases device yields. The Rapier XE allows recipe-controlled “tuning” of the etch profile to compensate for residual thickness non-uniformities introduced in earlier steps. Rapier XE supports ReVia™ the only end-point technology that can detect the Cu tips as they emerge from the Si surface. Collaborative work with imec has shown significant savings can be realised by controllably reducing via height to ~1µm, meaning that subsequent dielectric thickness and CMP removal times can be reduced.
- SPTS Website
- Date this Product was Introduced to the market: 05/22/2014
- Category Product is Being Nominated for: Processes
- Technical Information for Blanket Silicon Etch for TSV Reveal using Rapier XE
