Some people get excited when they go to Hollywood and see famous people. Not me. Today, I got positively giddy driving from from San Jose airport to both Invensas and Ultratech’s headquarters. Oh look! It’s SAMSUNG R&D CENTER! Toshiba! MICRON! I felt that I was in the presence of greatness. Yes – my inner geek is showing. But most of the time I’m working from my home in Arizona, just reading about all these places. Coming to Silicon Valley every once in a while gives me a chance to visit with the people who make this industry hum and become inspired to write about what I learn.
Today’s first stop was to Invensas, to meet with Simon McElrea. We had lunch, talked about where the industry is headed, and I had a tour of Invensas’ development lab in the Tessera facility. Here is where the xFD product family is put through its paces. They have it all, design and simulation, prototyping metrology, failure analysis, thermal cycling, drop testing, etc. Additionally, they partnered with European OSAT, Nanium to optimize the technology for commercialization and HVM readiness.
We talked about this one-year-young company’s pragmatic approach to technology development. While Invensas has made a significant investment in 3D IC development, the company takes the realistic perspective that 3D ICs are still a few years down the road before volume manufacturing (2015-2020). In the mean time, it makes sense to extend the life of existing package types through innovation. For example, the xFD memory platform comes in several configurations targeting different needs. The dual face-down package is optimized for denser, cheaper, faster servers. “There’s a lot more involved than just two chips face down. There’s an entire architecture to it,” notes McElrea. On the other hand, the quad face down has four overlapping die, was invented as a smaller way to package memory for next-generation notebook PCs that require increased functionality and huge amounts of memory in a thinner, lighter end product. The kicker is that the die are wire bonded, because as McErea explained, wire bond is still a viable interconnect, and there are other ways than TSVs to solve the density, performance and power issues. “When 3D arrives, it’s not like everything else dies,” he explained. “3D will be for the higher end applications, but it won’t replace everything.” He said it comes down to an adoption barrier. There floors full of wire bonders that manufacturers want to use. To just suddenly replace it with wafer processing equipment incurs massive incremental cost. Infusing the industry with innovative packages that leverage the existing infrastructure is a good way for a young IP company like Invensas to flex its muscles. And when 3D hits the big time, they’ll be in the game.
Second stop of the day was to see Manish Ranjan and Scott Zafiropoulo at Ultratech. As we usually do when we get together, we talked about the big picture of the packaging market, and the rapid introduction of next-generation end products (iPad 1, 2, 3) that are driving the ultimate need for 3D devices. Ranjan and I agreed that in the same way that WLP took less time to be adopted then flip chip, and eWLB tool less time than WLP because they all leveraged the process that preceded them, so will 3D TSV take less time than WLP because WLP has paved the way.
With its eye firmly on WLP and 3D packaging lithography processes in the back-end, the company is working diligently to stimulate technology adoption by addressing that massive incremental cost for equipment that McElrea was talking about. Ultratech’s current goal is to extend the product life cycle of its latest generation tools by extending the usefulness of the equipment, making it upgradable. For example, they intend to offer customers the opportunity to add such modules as dual side alignment which is necessary for the formation of TSVs.
According to Ranjan, 2011 turned out to be the best year in the history of the company in terms of bookings and revenue. They want to evolve their technology leadership into cost effective solutions to help accelerate the adoption of 3D packaging. I’ll drink to that.
To complete the spectrum of my day’s review of 3D, I visited Zvi Or-Bach at MonolithIC 3D headquarters. I’ve previously written about this company’s approach to concept for building 3D ICs, which differs fundamentally from 3D TSVs because it involves building up layers of silicon and metallization on a base wafer, rather than stacking die to die, die to wafer or wafer to wafer. MonolithIC 3D holds the patents to this technology, but the processes themselves are still in early stages of development. While many IP companies remain in stealth mode at this step of the process, Or-Bach prefers to take a different approach, by educating the industry about the company’s concepts in the hope that a manufacturing giant will license the technology and take it to completion. While the development is much further out than 3D TSVs, Or-Bach is confident that his company’s approach is actually much simpler and more cost efficient because it leverages existing fab equipment, and doesn’t require drilling vias through 50µm silicon wafers, which although it sounds simple, has proven to be a quite complicated and expensive process.
From 3D packaging to monolithic 3D, my day was complete. Tomorrow, I’ll be at EDPS in Monterey, getting the design perspective. I’ll keep you posted! ~ F.v.T.
