Latest Posts
Wafer-to-Wafer Bonding Cost Analysis
Last year, I did an analysis that included the topic of wafer-to-wafer bonding. Specifically, it was a comparison of the...
The Future of Image Sensors is Chip Stacking
CMOS image sensors (CIS) have often been heralded as the first 3D devices in volume manufacturing. However, this is not really...
Ziptronix: Copper DBI Technology for 3D Memory Assemblies
Product Description Copper DBI® technology is a patented low cost, scalable process technology that was licensed for 3D memory assemblies...SEMATECH Reports Advances in Bond Process for 3D Integration Development
With a focus on providing cost-effective and reliable solutions to accelerate manufacturing readiness of 3D technology options, SEMATECH experts reported...3D Discussion Topics: Looking for Member Input
I’ve been waging a campaign this week to bring in new members by contacting all the members of the...
3D R&D Round-up: MIT Lincoln Labs works on SOI
At MIT Lincoln Labs (MITLL), R&D processes developing 3D chips using silicon-on-insulator (SOI) wafers is the sole focus. As Phil...The post-fab process debate for 3D ICs: foundry or OSATS
Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking...CEA-Leti: A visit to the mother ship
If your company is located in France, and/or is involved in micro and nanotechnologies for microelectronics, chances are it’s...
