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Samsung VP to Keynote IWLPC
San Jose, California – USA – The International Wafer-Level Packaging Conference and Expo announces Dan Oh, Ph.D., Engineering VP of...IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller
There are several different fan-out wafer-level packaging (FOWLP) technologies that are currently in high-volume production. The traditional fan-out (FO) technology...Technical Tidbits from IWLPC and MSEC 2017
It’s been a busy few weeks for me as I attended both the International Wafer Level Packaging Conference (IWLPC), October...Panel Level Packaging: The Next Sleeping Giant? And Other Thoughts From IWLPC 2017
To the best of my recollection (and a quick search through 3D InCites’ archives) the panel level packaging (PLP) hoopla...High Productivity UBM/RDL Deposition by PVD for FOWLP Applications
Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a...IWLPC 3D Thursday: The Panel
It’s been a whirlwind of conferences these past few weeks, and as a result, I have attended FOUR panel discussions...IWLPC 2012: 3D Thursday Part 1
Today's 3D day kicked off with a very broad and thorough state-of-the-technology report from imec's perspective, presented by Paul Marchal. ...What’s in Store for 3D Fans at IWLPC 2010
I was so busy making sure I have all the bios and presentations for the 3D sessions I’m chairing at...Is the Bloom off the 3D TSV Rose?
So I’m sitting here back at my desk, sifting through my pile of notes from this week’s adventures at the...Georgia Tech’s Rao Tummala to deliver IWLPC Dinner Keynote
Trend and Progress from ICs to 3D ICs to 3D Systems-on-Wafer
This year's IWLPC dinner keynote address...
6th Annual IWLPC Program Set
The SMTA, in conjunction with Chip Scale Review magazine, is pleased to announce the program for our 6th Annual...