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Sir Walter Raleigh towered above the 50th IMAPS Symposium

Almost 500 years ago Walter Raleigh was born in England, rose rapidly in the favor of Queen Elizabeth I and was knighted in 1585. In 1587 he initiated the founding of Raleigh. Last week he welcomed – appropriately dressed – about one thousand semiconductor experts to the 50th International Symposium...

Solving the Design and Verification Challenges of High Density Advanced Packaging

Today’s electronic products present new challenges to product development teams. As a result, there is a constant push to improve product quality and design efficiency through the use of new design technologies. For example, system-scaling demands change as Moore’s law becomes increasingly difficult to maintain, thus driving growth of innovative...

Take-Aways from Test Vision 20/20 Workshop and SEMICON West Advanced Packaging Sessions

I am convinced that increasing device complexity, higher quality requirements (e.g. automotive and medical), as well as the need for faster production ramp-ups, will force our industry to pay even more attention to design-in quality, expand self-test, even add redundancy to control logic and interconnects. In addition, wafer-probe and final...

UnitySC Receives Multiple Orders for Wafer Thinning Inspection Systems

Grenoble, France, May 9, 2017 – UnitySC, a leader in advanced inspection and metrology solutions, today announced multiple orders from a leading integrated device manufacturer (IDM) for its modular 4See Series automated defect inspection platform. The systems were selected because they deliver optimal wafer backside surface and edge defect inspection,...

The FAST route to the Top of the TSV Mountain

. While on a recent visit to UnitySC in Grenoble, France, I spent some time visiting with a semiconductor process equipment company that shares the same cleanroom space: KOBUS. Named for a genus of the African antelope for its elegance and speed, the company has developed a unique approach to...

Using 3D Integration to Get the Heat Out

Thermal management is one of the last vestiges of 3D integration challenges. As such, the European 3D Summit (Jan 23-25, 2017) devoted its entire R&D segment to explore what is in the works to solve this in a session titled Tackling the Thermal Management Challenge. Chaired by Jean Michailos, STMicroelectronics...

The Edge of 3D: 3D SoC VLSI and Si Photonics

Last week, I posted an executive summary of this year’s European 3D Summit, touching on the highlights and general takeaways based on the closing remarks I delivered at this year’s well-attended event, which took place January 23-25, 2017 at Minatec Campus in Grenoble. In this post, we’ll take a deeper...

3D TSV IP Landscape for Memory Applications: Who Owns What?

The last two years have shown some important changes within the 3D through silicon via (TSV) memory market. First commercial products including 3D stacked (3DS), DDR4, high bandwidth memory (HBM) and hybrid memory cube (HMC) have been released by the microelectronics giants. Then first 3D TSV IP patent litigations took...

SEMICON Europa 2017 Moves to Munich

So here’s a funny story.  At the MEMS Summit in Stuttgart in September, while chatting with Denny McGuirk President and CEO, SEMI, I suggested that SEMICON Europa 2017 would be better attended if it was held in Munich. I’ll admit this was mostly selfishly motivated, as I’ve made the trek...