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Staying relevant in the ever-expanding technology landscape that is the semiconductor packaging industry can be a struggle for an event that’s been laser-focused on one emerging segment since its inception. But this past week, 3D Architectures for Semiconductor Integration and Packaging (3D ASIP 2015) delivered a program that not only addressed...
I’m not sure what it is about SEMI events held in the U.S. Northeast, but the last two I attended, ASMC 2015 (Saratoga Springs, NY), and the recent SEMI Northeast Forum on Power Electronics Manufacturing (Albany, NY), both reached full attendance capacity before they went live. Word must be out...
Multi-project wafer (MPW) programs have long been considered an economical way to integrate different IC designs from various teams to produce IC design prototypes and low volumes. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources in this way. MPWs were historically used...
Currently in advanced integration, mainly stacked solutions (Figure 1b) are considered due to their attractive compactness. But if the ASIC or the processor is a high-performance circuit, there are problems with the thermal budget of the stacked solution. This is because the valid temperature range of the memory is limited....
Yole Développement invites you to discover the main technology trends and business opportunities for 3D integration in 2015. As a research market & strategy consulting company, Yole Développement (Yole) works with the leaders of the advanced packaging industry every day to understand technical challenges and market issues. In this article,...
Years ago, when I gave my first 3D technology presentations, I noticed very different reactions from my diverse audience: The packaging engineers were in their element, engaged right away and asked detailed technical questions. The IC designers appeared quite worried about the strange — and for them, at that time...
Like the previous 10 years, RTI International held the 11th 3D-IC focused conference in early December. Instead of the usual two and a half days, this year it spanned 3 days, because it also offered a 4-hour session about 3D design challenges and solutions available from foundries, EDA and IP...
We’ve heard it expressed many times whenever there’s a new interconnect technology vying for adoption: manufacturers will select the best performing option at the lowest cost to do the job. However, as performance requirements reach previously un-anticipated levels, pitch requirements become tighter, and density requirements become higher, the job of...
Don’t miss a full morning of expert presentations about 3D-IC and Interposer design tools and methodologies! Since 2004, every December RTI International has organized a 3D technology focused conference in Burlingame, near the San Francisco Airport. Supply side industry experts presented the progress they had made in developing new manufacturing and...
One look at the agenda for the 11th Annual 3D Architectures for Semiconductor Integration and Packaging Conference (3D ASIP), and it becomes clear that this year the conference organizers have left no stone unturned. Kicking it off with Pre-conference Symposia that emphasize 3D design tools and flow and manufacturing processes,...
