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Putting 3D Integration to the Test

3D stacking is “already old hand”; or so declared Brion Keller, Cadence, in his keynote talk at last week’s 5th Annual 3D Test Workshop, which took place in Seattle, October 23-24, 2014. In his presentation, 3D Rock from the Sun, Keller talked about the wonders of technological progress, and how we...

GSA 3D IC Working Group Looks at 3D IC Readiness from Design through Manufacturing

At the recent GSA 3D IC Working Group Meeting (October 22, 2014), where speakers from BroadPak, Amkor, and Invensas presented on 3D IC readiness, I was struck by three observations. First of all, while challenges to 3D commercialization still remain, but they’ve shifted from manufacturing challenges to design and infrastructure...

IMAPS 2014: The Future of Packaging is System Integration

The annual International Microelectronics and Packaging Society (IMAPS) International Symposium has always focused more on advancements in mainstream packaging technologies, and left the emerging innovative processes to its spring event, the International Device Packaging Conference. As such, its speakers generally offered the most conservative viewpoints on 3D adoption. In a...

Are we Getting Mixed Messages on 3D IC Production?

While 3D IC production is underway for memory devices, some say demand for 3D ICs is still years away. Could both be right, or are we getting mixed messages? Today’s news from  SEMICON Taiwan, in which a DigiTimes reporter quoted Mike Liang, president of Amkor Technology Taiwan as saying that...

Will 2.5D and 3D Stacking Save the Semiconductor Industry?

Year’s ago, when I was managing editor of Advanced Packaging Magazine, each January issue featured an industry forecast cover story. For several years in a row, that issue predicted advanced packaging would be the key to improved performance at lower power and lower cost. January of 2007, we declared “Packaging...

Are there still Gaps in 3D IC Readiness?

Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words I’ve been waiting to hear her say for quite some time. “Memory stacks with TSVs are here!” Vardaman cited three companies actively involved in new memory architectures, all of which...

A Path Finding Based SI Design Methodology for 3D Integration

3D integration is being touted as the next semiconductor revolution by industry. 3D integration involves the use of various interconnects that include balls, pillars, bond wires, through silicon vias (TSV) and redistribution layers (RDL) for enabling chip stacking, interposer and printed circuit board (PCB) based technologies. More recently 2.5D integration...

2014 3D InCites Guide to 3D at SEMICON West

I can’t believe it’s already been a year since I last posted my annual guide to 3D at SEMICON West.  One thing I’ve noticed in scanning the “regulars” (SEMI and SEMI partner events) is that all the agendas are  much less focused on 3D integration developments. I think there are...

3D IC Adoption: What’s it going to Take?

If, as we heard at last week’s 3D IC Forum at SEMICON Singapore, that technology challenges and cost are no longer keeping 3D ICs from volume manufacturing, and indeed the key players are ready to go, then what’s it going to take to get this 3D IC adoption party started?...