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3D IC Implementation: Outlook for 2014

Mobile/smart devices will continue to drive innovation and volumes in the semiconductor industry in 2014. The much discussed “Internet of Things” is a vision for the next growth cycle, and while we see this vision eventually coming true, the industry is very early in the cycle. It will take a...

Notes from GIT 2013

The 3rd annual Global Interposer Technology Workshop (GIT 2013) was held at the Georgia Institute of Technology on November 18-20, 2013. Over 200 people from 11 countries attended this in-depth and lively discussion about interposers. Although many people think the conference is focused on glass (Glass Interposer Technology – another use...

IWLPC 2013: Will the Changing Mobile World Usher in 3D ICs?

…For while the tired waves, vainly breaking, Seem here no painful inch to gain, Far back, through creeks and inlets making, Comes silent, flooding in, the main…. (Excerpt from Say not the Struggle Naught Availeth, by Arthur Hugh Clough. 1819–1861) Sitaram Arkalgud, Invensas, quoted this verse to me yesterday over...

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling...

IMAPS International 2013

IMAPS International 2013 3D Technology Highlights

Approximately 880 people registered for IMAPS International 2013, and yes the fiasco in Washington even affected IMAPS – there were last minute cancellations from people who work directly or indirectly for the government. But I was there, and here are the highlights: Qualcomm : Vidhya Ramachandran presented data on a...

The Small Scale Systems Integration and Packaging (S³IP) Center

3D ICs for High Performance Systems

A recent IEEC and IEEE CPMT workshop held on October 16, 2013 at Binghamton University in New York examined the status of 2.5D and 3D ICs for high performance systems. There is no question that 3D ICs with through silicon vias (TSV) remain driven by concerns over astronomical lithography cost at...

Getting back to Basics: a Look at 3D NAND and 3D DRAM

There’s been a lot of buzz around 3D NAND in the past few weeks, sparked by Samsung’s recent announcement that it was commercializing its 3D VNAND technology. There’s also been some discussion (mixed with concern) about how, if at all, 3D NAND might affect the commercialization of TSV-based 3D DRAM...

3d NAND

Comparing Samsung’s 3D NAND with Traditional 3D ICs

At last week’s Memcon 2013, which took place Tuesday, August 6, 2013, at the Santa Clara Convention Center, Keynoter Bob Brennen, Senior VP at Samsung, talked about the need for New DRAM and Flash Memory architectures. Richard Goering summarized Brennan’s keynote very well in his blog post. Because Brennan’s responsibility...

Sum of Minds – imec Makes the Unexpected Happen

In her opening remarks at the 2013 imec International Technology Forum (ITF), held Monday, July 8, 2013,  Karen Savala, SEMI, said it best – this event, preceding SEMICON West, is a great way to set our mindset for the rest of the week. I couldn’t agree more.  What I have...

ECTC 2013 Interview: SPTS’s Keith Buchanan Addresses Bow and Warp

A few weeks ago I spoke with SPTS’s David Butler, after he participated in the SEMICON Singapore 3D IC panel. We talked a lot about the importance of wafer planarity for performing backside processes like TSV reveal.  Butler commented that regardless of a tool’s calibrated precision, its only as good...