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European 3D Summit 2018: Fraunhofer Tour and Presentations 

This year’s European 3D Summit in Dresden, which highlighted “Heterogeneous Integration Driving 3D”, was led off by presentations and a lab tour of the Fraunhofer Institute, whose 18 high-performance centers collaborate with companies, universities and other research institutes in Germany.  All pictures and diagrams courtesy of Fraunhofer IZM. The Fraunhofer...

Tech Session Highlights from ECTC 2017

Françoise promised in her recent blog that my ECTC blog would follow shortly. Finally, after attending DAC in Austin as well as the iMAPS’ SiP Conference in California’s Wine Country and shortly before attending Semicon West in San Francisco, I found some time to report what I saw and learned...

EV Group Breaks Speed and Accuracy Barrier in Mask Alignment Lithography for Semiconductor Advanced Packaging

FLORIAN, Austria, March 8, 2017—EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the IQ Aligner NT—its latest and most advanced automated mask alignment system for high-volume advanced packaging applications. Featuring high-intensity and high-uniformity exposure optics, new wafer...

13th 3D ASIP Conference Demonstrates Manufacturer’s Commitment

The 3D Architectures for Semiconductor Integration and Packaging (3D ASIP) conference is one of the biggest (if not THE biggest) event focused exclusively on the 3D IC family of technologies. The December 2016 event was held even closer to San Francisco airport than in previous years. From the lobby of...

Package-on-Package Interconnects for Fan-out Wafer Level Packages

Consumer electronics designers continue to demand thinner and lighter packages while devices increase in functional complexity. The Fan-Out Wafer Level Package (FOWLP) platform has been gaining momentum with the advantages it offers in electrical performance, assembly process efficiency and low geometric profile.  Different approaches of Package-on-Package (PoP) stacking in FOWLP...

The Commercialization of 3D Stackable Memory: Part One

The Challenges of Manufacturing 3D Stackable Memory Memory technologies vying to fulfill the increasing capacity and density requirements of the solid-state storage market two years from now will be confronted by having to meet demanding cell performance and cost-per-bit metrics to be viable. Today, NAND technology is still the primary...

2015 3D InCites Awards Winners

Reader’s Choice Award Amkor: SLIM Francoise von TrappJune 22, 2015 Awards-Devices, Awards-Winner0 Amkor’s SLIM (siliconless integrated module) is a dies-last package technology providing the thinnest possible form factor with the highest level of integration by use of back-end-of-line technology combined with assembly-based fan-out architectures.  It has optimal registration, 3D access to...