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For the 8th year in a row, I did NOT attend SEMICON Singapore. But apparently this is the year I should have been there to cover the 3D IC Forum, as it was well attended and had a robust program with 15 speakers and a panel discussion (at least that’s...
For me, the most exciting news so far at this year’s 3D ASIP conference has been the announcement that Tezzaron Semiconductor is licensing both Ziptronix’s Zibond and DBI technologies . Really, I did backflips when I read the press release, because I have a soft spot for technology innovators and...
SPTS Technologies has launched its low temperature plasma-enhanced chemical vapor deposition (PECVD) solution for via-reveal passivation in 3D-IC packaging applications. Already proven in 300mm volume production fabs, the Delta fxP® PECVD system deposits dielectric layers onto bonded substrates at wafer temperatures below 200°C, with throughputs up to twice that of...
There's no place like SEMICON West for a company to make a major announcement. After all, it is the semiconductor industry's annual 'coming out party'. My inbox was flooded with press releases this morning, and since my flight was delayed so much that I completely missed the SEMI press conference,...
Outsourced Semiconductor Assembly and Test (OSAT) provider, STATS ChipPAC Ltd., has announced qualification of its 300mm middle-end-of-line (MEOL) manufacturing operation for Through Silicon Via (TSV) capabilities, and will transition to low volume manufacturing. STATS ChipPAC says it is firmly engaged with multiple strategic customers on TSV development programs that support the...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
Coverage of the GSA Memory Conference continues in this week's issue of Chip Scale Review Tech Monthly. Francoise von Trapp contributed this article. While there continue to be incremental improvements and innovations in single chip packaging technologies, it’s nothing compared to the focus on multi-chip assembly and packaging technologies. Whether...
Keith Cooper, Technology and Development, SET North America reports from 2010 IMAPS International , where he attended the 3D Panel, “Roadmap, Technical and Business Progress of 3D Integration and Packaging”. At the recent IMAPS Annual Meeting in Raleigh, NC, a panel of 3D experts addressed a series of questions moderated...
Reporting progress for CEA-Léti was 3D program manager Mark Scannell, who notes an overall shift in what’s driving Léti's 3D developments.
If your company is located in France, and/or is involved in micro and nanotechnologies for microelectronics, chances are it’s either a spin out of Leti, its parent organization CEA, or is closely tied in ongoing collaboration to this major European research center for applied electronics. At least that is...
