Matches for your search: "hybrid bonding "
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
EV Group (EVG) supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced the completion of its newly expanded cleanroom IV facility at its corporate headquarters in Austria. As part of the company's long-term growth strategy to address high-volume tool orders and speed time to...
We read a lot about the remaining challenges to be addressed before 3D ICs are fully commercialized. Current roadmaps are now targeting 2015 for commercialization of 3D ICs, while 2.5D gets the ball rolling towards the end of 2012, beginning of 2013. Reports from Xilinx indicate they are shipping 2.5D...
Redesigned, Fully Automated Modular System Integrates Unmatched Spray Coating Processes for MEMS, Compound Semiconductors and Advanced Packaging SEMICON TAIWAN, Taipei, September 4, 2012 - EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled its next-generation EVG150 automated resist...
After seeing the latest press release on Ziptronix foray into the memory space, I sought out Kathy Cook, business development manager at Ziptronix, at ECTC to get the full story. We’ve been reading and hearing a lot about Ziptronix ZiBond process being used in CMOS image sensor (BSI) technology, and particularly...
Last time I visited Leti on the Minatec Campus was in October 2009. Recently, when I was back for Leti’s Annual Research Reviews, Mark Scannell, head of the 3D integration program, took me on another tour. A lot has been going on here in the past 2 years. For one...
At last month’s 3D Architectures for Semiconductor Integration and Packaging Conference, coordinated by RTI International, three government-funded research institutes – RTI, CEA-Leti, and MIT Lincoln Laboratories reported on the status of their progress in the 3D integration space.
SEMICON Singapore gets underway next week (May 19-21), and the 3D track speaker line-up features presentations by several 3D InCites partners. If you plan on attending, be sure to put these sure-to-be interesting talks on your personal agenda.
This year’s 2010 IEEE International Interconnect Technology Conference (June 7-9, Burlingame, CA) has caught the 3D fever.
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are vital to a multitude of semiconductor applications such as MEMS, compound semiconductors, LEDs, fan-out WLP, CMOS image sensors (CIS) and most recently, 3D IC using TSV interconnects.
