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Novel Multi-die Integration Concept Offers Big Benefits

The monthly MEPTEC Luncheons at SEMI in Milpitas focus on microelectronics packaging and test topics. Javier DeLaCruz, Xperi’s VP of Engineering, presented at the latest Luncheon on January 8 a joint study with eSilicon. It compared how die-to-wafer (D2W) bonding, using Direct Bonding Interconnect (DBI) technology, compares with traditional (2.5/3D-IC)...

A Look Inside The 3D Technology Toolbox For STCO

System-technology co-optimization (STCO) – enabled by 3D integration technologies – is seen as a next ‘knob’ for continuing the scaling path. In this article, we will unravel the STCO principle, open up the 3D technology toolbox and bring up two promising cases: logic on memory, and backside power delivery. After DTCO...

SETNA: Process for Room Temperature 3D IC Assembly

SETNA, in conjunction with Research Triangle Institute (RTI), has developed a binary alloy (Silver-to-Indium) bonding system for 3D IC assembly that can be compression-bonded at room temperature. Following 3D IC chip stacking, the Ag-In structure is annealed in the solid-state (no melting) to form an Ag₂In interconnect which is stable...

3D Readiness Report Card

3D ASIP 2013: Jan Vardaman’s 3D Readiness Report Card

While other presenters for the 2013 3D ASIP session, “Evolution of 3D Technologies and Market Trends” took a more conventional approach to reporting the status of 3D integration, Jan Vardaman, TechSearch International gets the prize for originality and humor for playing the role of “professor” and delivering the 3D readiness...

SUSS MicroTec Announces Follow-up Order for 300mm Bonding Tools for HVM 3D ICs

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets has received a follow up purchase order for the latest generation of high volume manufacturing temporary bond clusters from a world-leading IDM (Integrated Device Manufacturer). The customer, who  installed SUSS MicroTec tools in 2012, plans...

SEMATECH Reports Advances in Bond Process for 3D Integration Development

With a focus on providing cost-effective and reliable solutions to accelerate manufacturing readiness of 3D technology options, SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual Device Packaging Conference (DPC) on March 7-10 in Scottsdale, AZ. Technologists from SEMATECH’s 3D Interconnect program have demonstrated a novel die-to-wafer...

EV Group: Progress on Advanced C2W Bonding

When it comes to 3D chip stacking, chip-to-wafer (C2W) processes have proven to be the way to go for stacking known-good-die (KGD) for best yields, or if the dies being stacked are of different size. Unfortunately, sequential C2W processes have historically been time consuming, achieving low throughput; making it a...

Rudolph Technologies Collaborates in 3D Advanced Packaging Integration

Rudolph Technologies, Inc., provider of process characterization equipment and software for wafer fabs and advanced packaging facilities announced  that it will collaborate with a process tool supplier and an IC device manufacturer in the development of 3D advanced semiconductor packaging applications. The development effort involves the integration of defect inspection...