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SAN JOSE, Calif.—July 10, 2024—Adeia Inc. (Nasdaq: ADEA), a leading research and development and intellectual property licensing company known for bringing innovations in the semiconductor and media technology sectors to market, was awarded Best Session Paper at the 2024 Electronic Components and Technology Conference (ECTC) held in Denver, Colorado on...
Adeia Inc., a leading R&D and intellectual property (IP) licensing company known for bringing leading innovations in the semiconductor and media/entertainment technology sectors to market, announced recent developments in hybrid bonding, a technology targeted toward the future of semiconductor packaging enabling high-performance computing capabilities, like those required for AI. The...
Experience higher integration density and improved performance through hybrid bonding techniques. Denver, Colorado – May 23, 2024 – Brewer Science, Inc., a pioneer in temporary and hybrid bonding materials for the advanced packaging semiconductor industry, is presenting and exhibiting at Electronic Components and Technology Conference (ECTC) May 28th through May 31st, 2024. Challenges for High...
The rapid rise of new artificial intelligence (AI) applications — boosted recently by broad interest in generative AI (GenAI) — is dramatically impacting the semiconductor industry. It is accelerating demand for compute capacity that will outpace the capabilities of current chipset technologies underpinning today’s high-performance infrastructures, platforms, and devices, according...
Sorry for the disruption of the chronological flow of my recent blogs, but before I move on to the July coverage of the much-anticipated IMAPS “ONSHORING” conference, I wanted to continue covering a few of the papers from the 2023 IMAPS Device Packaging Workshop, which took place in March. As...
A Technology Chasm Until recently, the world of IC fabrication was neatly divided into the distinct stages of front-end and back-end processing, with a large chasm separating them for both process complexity and economic value. The front end has been focused on increased processing or computing power and achieves this...
IME – Hybrid Bonding Studies Singapore’s Institute of Microelectronics – IME / AStar – was certainly the most prolific presenter at the conference. In their presentation, “Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies”, they review in great detail processing issues prevalent in hybrid bonding. Wafer-level fine-pitch hybrid bonding, first...
Requirements for interconnect pitches of 20µm and below is expected to be the norm in the future. Since typical solder bump technology is not expected to be able to meet those requirements, many companies have been examining Cu-to-Cu direct bonding. Cu-to-Cu bonding can be achieved through one of two ways:...
Hybrid bonding is quickly becoming recognized as the preferred permanent bonding path for forming high-density interconnects in heterogeneous integration applications, from 2DS enhanced, to 3D stacking with or without through silicon vias (TSVs), as well as MEMS and III-V applications. In this exclusive interview with Gill Fountain, Xperi, winner of...
Enables fine-pitch connections for 3D applications, including image sensors, memory and 3D SoCs RESEARCH TRIANGLE PARK, N.C., May 27, 2014 – Ziptronix Inc. and EV Group (“EVG”) today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers. The results were achieved by implementing Ziptronix’s DBI®...
