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Presentations to highlight breakthrough capabilities of EVG’s maskless lithography, hybrid bonding and IR laser release solutions for heterogeneous integration; EVG sees continued strong growth in region EV Group (EVG) today announced that it will highlight key advances in 3D integration process solutions, including hybrid and fusion wafer bonding, infrared (IR)...
The dedicated HVM EVG®880 LayerRelease™ system boosts productivity and lowers the cost-of-ownership of novel infrared laser release technology through silicon carrier wafers for 3D integration applications EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology, and semiconductor markets, today introduced the EVG®880 LayerRelease™...
An AI package is like a puzzle made up of individual pieces of different sizes and shapes, each one essential to the final product. Together, these pieces are typically integrated into a 2.5D IC package designed to reduce footprint and maximize bandwidth. A graphic processing unit (GPU) and multiple 3D...
Expanded collaboration includes installation of EVG’s LITHOSCALE® maskless exposure system, EVG®7300 UV-NIL system and complementary resist processing systems FLORIAN / GRAZ, Austria, November 13, 2023—EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and Silicon Austria Labs (SAL), Austria’s leading...
ST. FLORIAN, Austria, November 7, 2022—EV Group (EVG), a leading provider of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has strengthened its portfolio of optical lithography solutions with the unveiling of the next-generation 200-mm version of its EVG®150 automated resist processing...
“The time has come when we have to understand that we can only compete WHEN we collaborate.” (Sudipto Roy, SMIC, at ECTC 2013, May 2013.) In part 1 of this article, we covered some of the challenges dealing with the business of complex 3D IC supply chains in a conversation...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
SPTS Technologies has launched its low temperature plasma-enhanced chemical vapor deposition (PECVD) solution for via-reveal passivation in 3D-IC packaging applications. Already proven in 300mm volume production fabs, the Delta fxP® PECVD system deposits dielectric layers onto bonded substrates at wafer temperatures below 200°C, with throughputs up to twice that of...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
SEMI announced today the formation of a Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee. 3DS-ICs are composed of a stack of two-dimensional die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration methods like wirebond and flip chip have been in production...
