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Learning about Plasma Technology Hands-on Through an Internship at Trymax

Hello, I am Mandy Perdok. I am 20 years old and live in Milsbeek in the Netherlands. My hobbies include playing Netball (Team Sport), training/coaching the Netball youth team, and traveling. As a third-year student majoring in Chemical Engineering at the Fontys Hogeschool Eindhoven of Applied Science, I am completing...

ClassOne Technology and Fraunhofer ENAS to Collaborate on Hybrid Bonding for Advanced Imaging Devices

Partnership will leverage firms’ respective heterogeneous-integration proficiencies to focus on development and optimization of full process-integration schemes for diverse high-density pixel array applications  Kalispell, Mont. – June 2, 2022 – ClassOne Technology, a leading global provider of advanced electroplating and wet processing tools for microelectronics manufacturing, today announced it is...

Smoltek demonstrates CNF-growth on a 200mm silicon wafer

Last week our awesome and hardworking R&D-team managed to demonstrate CNF-growth on a 200mm silicon wafer in the Chalmers MC2 150mm lab in Gothenburg. This great achievement opens up new methods for better and simpler prototype manufacturing for customers utilizing 200mm production processes.

SPTS Debuts Low-Temperature PECVD Technology for 3D-IC

SPTS Technologies has launched its low temperature plasma-enhanced chemical vapor deposition (PECVD) solution for via-reveal passivation in 3D-IC packaging applications. Already proven in 300mm volume production fabs, the Delta fxP® PECVD system deposits dielectric layers onto bonded substrates at wafer temperatures below 200°C,  with throughputs up to twice that of...

SEMI International Standards Program Forms 3D Stacked IC Standards Committee

SEMI announced today the formation of a Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee. 3DS-ICs are composed of a stack of two-dimensional die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration methods like wirebond and flip chip have been in production...

SEMATECH Technologists Detail Process Advances to Accelerate 3D Manufacturing Readiness

With a focus on providing cost-effective and reliable solutions to speed manufacturing readiness of 3D technology options, experts from SEMATECH’s 3D interconnect program based at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex outlined new developments in wafer bonding, copper removal, and wafer thinning at the 2010...