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EV Group Brings Maskless Lithography to High-volume Manufacturing with LITHOSCALE

LITHOSCALE® incorporates EVG’s MLE™ (Maskless Exposure) technology to bring the benefits of digital lithography to a wide range of applications and markets EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the LITHOSCALE® maskless exposure system – the...

EV Group’s MLE Technology Revolutionizes Lithography

EV Group (EVG) today unveiled its maskless exposure technology (MLE™), a revolutionary next-generation lithography technology developed to address future back-end lithography needs for advanced packaging, MEMS, biomedical and high-density printed circuit board (PCB) applications. The world’s first highly scalable maskless lithography technology for high-volume manufacturing (HVM), MLE combines high-resolution patterning...

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced layout vs. schematic (LVS)-like verification techniques that can move...

DAC 54: From Grey to Colorful and Solutions-minded Messaging

The 54th Design Automation Conference (DAC 54) at the Austin Convention Center was very different, compared to the last several years’ events. Walking the exhibition floor, listening to keynotes, SKY talks and CEO interviews I got the following key impressions: While still representing a big part of the audience, the...

Challenges and Solutions for EDA of 3D Chip Stacks

It is often claimed that 3D chip stacks offer the potential to meet current and future requirements of digital circuits, such as for performance, functionality, and power consumption. Specifically, both design paradigms “More Moore” and “More than Moore” will benefit from 3D chip stacking (and new technologies and materials). 3D...

Why is it Taking so Long to Ramp Interposer and 3D IC Designs?

And what are we going to do about it in 2015…? A moment ago I finished reading my predictions for 2014. I wrote them on January 11, 2014, almost exactly one year ago. After convincing myself that I was roughly on target, I am going to stick my neck out again,...

2015 Industry Outlook: SPTS Predicts its 3D Etch, PVD and CVD will reach HVM

In June 2014, SPTS co-produced a webinar with Ron Huemoeller of Amkor, titled “2.5D and 3D Packaging at the Tipping Point.” We forecasted that significant product announcements would be made over the next 18 months and we were right; sk Hynix, Samsung and Micron all announced readiness for their 3D stacked memory...

Semi Trade Pubs Talk 3D, Just in time for SEMICON West

That Jan Vardaman, she’s so clever! I just finished reading her column on ECTC 2013 in Printed Circuit Design and Fab, and thought her quippy, Las Vegas-y references in the opening paragraph were right on the money. Vardaman’s take on ECTC was similar to my own, discussed here in my...

3D TSV Summiit

European 3D TSV Summit: But Wait, There’s More!

Day Two of the European 3D TSV Summit dawned bright and clear, with such a spectacular view of the nearby French Alps that it took real commitment to stay indoors and focus on the task at hand. But I have to admit that for the most part, it was worth...

Applied Materials Announces Atomic-Level Film Treatment to Reduce Chip Power Consumption

Applied Materials, Inc. today announced a breakthrough technology for reducing power consumption in semiconductor chips with its new Applied Producer® OnyxTM film treatment system. By optimizing the molecular structure of the low k films that insulate the miles of wiring, or interconnects, on each chip, the Producer Onyx system enables customers to continue...