Search Results

Matches for your search: "fan-out wafer level packaging "

SEMICON West… It’s Back! Community Member Preview

We presume all are excited about the upcoming SEMICON West show. I know we sure are! Be sure to stop by the 3D InCites booth #731 and say hi or if you are walking by the SEMI booth Francoise may be in action recording a Podcast, acting as the official...

CyberOptics to Present Fast, 100% Wafer Bump Metrology and Inspection at Virtual IEEE PAINE Conference

Minneapolis, Minnesota— November 18th, 2020 — CyberOptics® Corporation a leading global developer and manufacturer of high-precision 3D sensing technology solutions, will present at the Virtual IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) on December 16th at 8:00amCT. Tim Skunes, VP of R&D at CyberOptics, will share the technical presentation...

Semiconductor Back End Processes: Adopting GEM Judiciously

Equipment Communication Leadership in Wafer Fabrication For many years the semiconductor industry’s wafer fabrication facilities, where semiconductor devices are manufactured on [principally] silicon substrates, have universally embraced and mandated the GEM standard on nearly 100% of the production equipment. This includes the complete spectrum of front-end-of-line (FEOL – device formation)...

Cost Analysis of a Wet Etch TSV Reveal Process

Through silicon via (TSV) technology is a key design element being incorporated into more and more advanced packaging designs today. TSVs offer distinct benefits in form factor and improved performance and can enable new, innovative designs not previously possible. To scale this valuable technology and spark industry adoption, there is...

SPTS Technologies’ Silicon Etch Tool Chosen for 300mm CMOS Image Sensor Applicatons

Move to 300mm Strengthens Customer’s Position in the Rapidly Growing CMOS Image Sensor Market Newport, United Kingdom, 29 May, 2014 – SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced that a leading Chinese wafer level packaging (WLP) supplier to...

2.5D Interposer wafer - TSMC

Motivation for 3D IC and other Key Take-Aways from the IEEE 3D IC Conference

The IEEE 3D Systems Integration Conference (IEEE 3D IC) is a unique event that is a truly international effort in assembling all those involved in research and commercialization of 3D IC and 3D systems from around the world. Location for the event rotates annually from Munich to Tokyo to San Francisco. This...

Dynaloy: A Formula for Cleans

It’s hard to believe that inside such a non-descript building set back down a picturesque country lane in (almost) rural Indiana, really cool things are happening. This is the home of Dynaloy, LLC, a subsidiary of Eastman Chemical Company, where innovative chemical formulations are being developed to remove the most...

ASMC 2013 and 3D IC: Time to Volume, Time to Via

What is today’s biggest threat to continued growth in the semiconductor industry? Subramani Kengeri, Vice President, Advanced Technology Architecture, GLOBALFOUNDRIES, opening the 24th annual SEMI Advanced Semiconductor Manufacturing Conference in Saratoga Springs, NY, asked just that question in his keynote address. (Asked it twice, actually; once at the beginning of...

3D TSV Summiit

European 3D TSV Summit: Focus on Cost of Ownership

Now that the “technology bricks” for building 2.5D devices and 3D ICs have been essentially qualified, the focus has turned to optimizing them for improved cost of ownership (CoO).  At last week’s European 3D TSV Summit, in Grenoble, France, many of the supplier presentations demonstrated how their companies have been...

3D IC Pioneers Continue to Lead the Way

For me, the most exciting news so far at this year’s 3D ASIP conference has been the announcement that Tezzaron Semiconductor is licensing both Ziptronix’s Zibond  and DBI technologies . Really, I did backflips when I read the press release, because I have a soft spot for technology innovators and...