Search Results

Matches for your search: "fan-out wafer level packaging "

EV Group Brings Revolutionary Layer Transfer Technology to High-volume Manufacturing with EVG®850 NanoCleave™ System

Dec 07, 2023

Infrared laser cleave technology enables ultra-thin-layer transfer from silicon substrates with nanometer precision, revolutionizing 3D integration for advanced packaging and transistor scaling FLORIAN, Austria, December 7, 2023—EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG®850 NanoCleave™...

Emerald Rapids

IFTLE 560: Emerald Rapids – Is Intel Backing off on Chiplets?

Jun 27, 2023

A recent report by Semi Analysis (SA) notes that Intel has backed off on the use of chiplets in its 5th Generation Xeon Scalable Processor Emerald Rapids (EMR). SA reports that at a recent Intel webinar, VP Sandra Rivera revealed that EMR, Intel’s 5th Generation Xeon Scalable Processor, had backtracked...

SEMICON West… It’s Back! Community Member Preview

Dec 02, 2021

We presume all are excited about the upcoming SEMICON West show. I know we sure are! Be sure to stop by the 3D InCites booth #731 and say hi or if you are walking by the SEMI booth Francoise may be in action recording a Podcast, acting as the official...

Semiconductor Back End Processes: Adopting GEM Judiciously

Jul 01, 2020

Equipment Communication Leadership in Wafer Fabrication For many years the semiconductor industry’s wafer fabrication facilities, where semiconductor devices are manufactured on [principally] silicon substrates, have universally embraced and mandated the GEM standard on nearly 100% of the production equipment. This includes the complete spectrum of front-end-of-line (FEOL – device formation)...

SPTS Technologies’ Silicon Etch Tool Chosen for 300mm CMOS Image Sensor Applicatons

Jun 02, 2014

Move to 300mm Strengthens Customer’s Position in the Rapidly Growing CMOS Image Sensor Market Newport, United Kingdom, 29 May, 2014 – SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced that a leading Chinese wafer level packaging (WLP) supplier to...

2.5D Interposer wafer - TSMC

Motivation for 3D IC and other Key Take-Aways from the IEEE 3D IC Conference

Oct 07, 2013

The IEEE 3D Systems Integration Conference (IEEE 3D IC) is a unique event that is a truly international effort in assembling all those involved in research and commercialization of 3D IC and 3D systems from around the world. Location for the event rotates annually from Munich to Tokyo to San Francisco. This...

Dynaloy: A Formula for Cleans

Aug 21, 2013

It’s hard to believe that inside such a non-descript building set back down a picturesque country lane in (almost) rural Indiana, really cool things are happening. This is the home of Dynaloy, LLC, a subsidiary of Eastman Chemical Company, where innovative chemical formulations are being developed to remove the most...

ASMC 2013 and 3D IC: Time to Volume, Time to Via

May 28, 2013

What is today’s biggest threat to continued growth in the semiconductor industry? Subramani Kengeri, Vice President, Advanced Technology Architecture, GLOBALFOUNDRIES, opening the 24th annual SEMI Advanced Semiconductor Manufacturing Conference in Saratoga Springs, NY, asked just that question in his keynote address. (Asked it twice, actually; once at the beginning of...

Filled vs. conformal vias: the consensus

Oct 06, 2009

Dr. Zhang, I think we have reached a verdict.

Bob Patti wrote in to confirm Anonymous Caller’s statement regarding polymer-filled, copper-lined TSVs, and also provided some additional data to support his comments. I’ve taken the liberty of paraphrasing his comments here:

With the caveat that he...