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Latest Generation Front-end Cleaning Tool Reduces Chemical Use by 75% ACM Research, Inc., a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging applications, today announced a major performance breakthrough for its flagship Ultra C Tahoe Cleaning tool. The resulting enhancements are designed to meet demanding technical...
Continuing our coverage of ECTC 2021, let’s take a look at the session on Heterogeneous Integration (HI) using 2.XD/3D packaging, chaired by Subash Shinde of Notre Dame and John Knickerbocker of IBM. IBM Introduces Direct Bonded HI Si Bridge Technology Though they are not manufacturing chips or packages anymore, IBM...
Nimes, France, April 15, 2016 – FOGALE Nanotech today announced that it has acquired Altatech, a specialized technology leader in the development of wafer inspection and material deposition tools for semiconductor manufacturing. Altatech SAS has headquarters in Grenoble, France, located in the center of the French Silicon Valley with a...
Eric Beyne (imec) and I go way back. He’s the Scientific Director of Advanced Packaging Technologies at imec, and ever since my Advanced Packaging days, he’s been a valuable resource whenever I have technology questions about any part of the spectrum of 3D integration technologies. Basically, I can count on...
To enable high-volume production readiness of 3D-based products, SEMATECH’s 3D Interconnect and Manufacturability programs will be conducting Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high volume manufacturing maturity issues. The assessment is a cooperative effort among experts from SEMATECH’s...
The official inauguration of STATS ChipPAC’s 300mm eWLB facility was held September 15, at the company's Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating. In April of 2010, STATS ChipPAC established itself as the first in the world to implement 300mm...
New System Provides World-class Alignment Technology at an Affordable Cost
Semiconductor test and advanced packaging service provider (SATS) STATS ChipPAC announced it has has expanded embedded Wafer-Level Ball Grid Array (eWLB) technology -- jointly developed by STATS ChipPAC, Infineon, and ST Microelectronics -- to reconstituted 3
At MIT Lincoln Labs (MITLL), R&D processes developing 3D chips using silicon-on-insulator (SOI) wafers is the sole focus. As Phil Garrou, Ph.D.
EV Group (EVG) and Applied Materials, Inc. announced a joint effort to develop wafer bonding processes for the manufacture of TSVs for 3D IC packaging applications. The two companies will be working together as members of the EMC-3D Semiconductor 3D...
