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YES Panel-Level Through Glass Via (TGV) Etch Tool Placed in Production

YES, a leading manufacturer of process equipment for semiconductor advanced packaging, life sciences, and AR/VR applications, today announced that its TersOnus TGV tool was released for panel-level manufacturing. This system will be used to support the growth of advanced heterogeneous packaging for artificial intelligence chips that enable large language models....

design-for-test

Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D

Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices.  These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or...

Leaders in Semiconductors, Packaging, IP Suppliers, Foundries, and Cloud Service Providers Join Forces to Standardize Chiplet Ecosystem

BEAVERTON, Ore.–(BUSINESS WIRE)–Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company today announced the formation of an industry consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The organization, representing a diverse...

Will Fully Autonomous Vehicles Solve Global Transportation Problems?

Automotive electronics, with the Holy Grail being fully autonomous vehicles, is currently being touted as one of the biggest growth drivers for the semiconductor industry. So much so, that every event I’ve attended so far this year has featured sessions, presentations, keynotes, and panel discussions espousing the benefits of autonomous...

System-level Scaling: UCLA’s Answer to Extending Moore’s Law

“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about...

Path Finding Series Part 3: The Cost of Non-robust Design

In previous posts, I discussed a process for process-centering a design. In this post, we will examine how non-robust design’s erratic yields can impact the manufacturing environment and cost of a product. A non-robust design will have at least one specification that is skewed away from the specification’s center as...

An Open Letter to Chip and System-level Designers Regarding 3D Integration

Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known in the semiconductor industry as “The Queen of 3D”. This is because I have held a deep interest in 3D integration technologies, and have devoted the past 7+ years to...

Bluebird: A project in 3D Equipment Development

I consider myself to be fairly savvy when it comes to knowing who the players are in 3D IC technology research, so when I first saw the news article in EDN reporting that TNO, an Eindhoven-based scientific research company, had approached BESI/Datacon to develop a high-end pick-and place tool for...

Musings From SEMICON West 2012

Tish LeBlanc, from TI: "How's your SEMICON West going? Me: "I was just trying to put it into words." It's Thursday, and another SEMICON West (my seventh) is winding down, and its the first time I've found time to write since Monday evening. As always, it's been a whirlwind of...

Monolithic 3D: A Basic Primer

Ever since I put on the editorial director hat for 3D-ICs.com, which aggregates 3D technology news, blogs and papers, and categorizes them as either TSV and 3D packaging or monolithic 3D, I’ve been trying to wrap my head around the differences between 3D TSVs and monolithic 3D integration technologies.  I’ve...