Matches for your search: "fan-out wafer level packaging "
A recent report by Semi Analysis (SA) notes that Intel has backed off on the use of chiplets in its 5th Generation Xeon Scalable Processor Emerald Rapids (EMR). SA reports that at a recent Intel webinar, VP Sandra Rivera revealed that EMR, Intel’s 5th Generation Xeon Scalable Processor, had backtracked...
In previous posts, I discussed a process for process-centering a design. In this post, we will examine how non-robust design’s erratic yields can impact the manufacturing environment and cost of a product. A non-robust design will have at least one specification that is skewed away from the specification’s center as...
I consider myself to be fairly savvy when it comes to knowing who the players are in 3D IC technology research, so when I first saw the news article in EDN reporting that TNO, an Eindhoven-based scientific research company, had approached BESI/Datacon to develop a high-end pick-and place tool for...
Eric Beyne (imec) and I go way back. He’s the Scientific Director of Advanced Packaging Technologies at imec, and ever since my Advanced Packaging days, he’s been a valuable resource whenever I have technology questions about any part of the spectrum of 3D integration technologies. Basically, I can count on...
Tish LeBlanc, from TI: "How's your SEMICON West going? Me: "I was just trying to put it into words." It's Thursday, and another SEMICON West (my seventh) is winding down, and its the first time I've found time to write since Monday evening. As always, it's been a whirlwind of...
Ever since I put on the editorial director hat for 3D-ICs.com, which aggregates 3D technology news, blogs and papers, and categorizes them as either TSV and 3D packaging or monolithic 3D, I’ve been trying to wrap my head around the differences between 3D TSVs and monolithic 3D integration technologies. I’ve...
The official inauguration of STATS ChipPAC’s 300mm eWLB facility was held September 15, at the company's Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating. In April of 2010, STATS ChipPAC established itself as the first in the world to implement 300mm...
New System Provides World-class Alignment Technology at an Affordable Cost
Semiconductor test and advanced packaging service provider (SATS) STATS ChipPAC announced it has has expanded embedded Wafer-Level Ball Grid Array (eWLB) technology -- jointly developed by STATS ChipPAC, Infineon, and ST Microelectronics -- to reconstituted 3
EV Group (EVG) and Applied Materials, Inc. announced a joint effort to develop wafer bonding processes for the manufacture of TSVs for 3D IC packaging applications. The two companies will be working together as members of the EMC-3D Semiconductor 3D...
