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YES, a leading manufacturer of process equipment for semiconductor advanced packaging, life sciences, and AR/VR applications, today announced that its TersOnus TGV tool was released for panel-level manufacturing. This system will be used to support the growth of advanced heterogeneous packaging for artificial intelligence chips that enable large language models....
MILPITAS, Calif. — May 8, 2024 — SEMI today released the report A Rising Tide: Building a Climate-Resilient Semiconductor Value Chain that spotlights the maturity of the semiconductor value chain as it strives toward greater climate resilience and develops climate risk mitigation strategies. Led by the SEMI Sustainability Initiative Environmental Risk Mitigation and Reporting (ERMR)...
Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices. These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or...
BEAVERTON, Ore.–(BUSINESS WIRE)–Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company today announced the formation of an industry consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The organization, representing a diverse...
The 2019 3D InCites Awards vote was a nail-biter right up until the end. While some categories seemed almost predictable from start, others were neck-and-neck, with the front runner changing on a daily basis. What was most exciting to me, however, was how many new participants we had, and how...
Automotive electronics, with the Holy Grail being fully autonomous vehicles, is currently being touted as one of the biggest growth drivers for the semiconductor industry. So much so, that every event I’ve attended so far this year has featured sessions, presentations, keynotes, and panel discussions espousing the benefits of autonomous...
“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about...
Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known in the semiconductor industry as “The Queen of 3D”. This is because I have held a deep interest in 3D integration technologies, and have devoted the past 7+ years to...
I consider myself to be fairly savvy when it comes to knowing who the players are in 3D IC technology research, so when I first saw the news article in EDN reporting that TNO, an Eindhoven-based scientific research company, had approached BESI/Datacon to develop a high-end pick-and place tool for...
With two 3D focused keynotes and a 3D panel discussion, 3D Thursday was ripe for the tweeting. The sound bites were coming fast and furious from Subu Iyer, IBM Fellow, and Rao Tummala, director of Georgia Tech’s 3D Packaging Research Center. Additionally, the 3D Panel featuring both Iyer and Tummala,...
