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ClassOne Technology Ships Follow-on Solstice® S8 Single-Wafer Processing System to Leading Aerospace and Defense Company

May 04, 2023

ClassOne Technology, a leading global provider of advanced electroplating and wet processing tools for microelectronics manufacturing, today announced it has shipped another Solstice® CopperMax™ single-wafer processing system to a leading provider of aerospace and defense solutions. Built on ClassOne’s state-of-the-art, high-throughput Solstice platform, the system will augment the customer’s existing installed...

Worldwide Silicon Wafer Shipments Set New Record in Q3 2022, SEMI Reports

Oct 26, 2022

MILPITAS, Calif. — October 25, 2022 — Worldwide silicon wafer shipments reached a new record of 3,741 million square inches (MSI) in the third quarter of 2022, increasing 1.0% quarter-over-quarter and growing 2.5% from the 3,649 MSI recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG)...

ACM Research Receives Multiple Purchase Orders for Ultra C wb Wet Bench Tools

Feb 13, 2022

Largest purchase order for wet bench systems in ACM’s history; Wet bench product line expanded to include Ultra-Low-Pressure Dry (ULD) technology FREMONT, Calif., Feb. 13, 2022 (GLOBE NEWSWIRE) — ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) applications,...

IFTLE 459: imec Develops Nano-TSV for Heterogeneous Integration

Aug 24, 2020

This week we continue our look at ECTC 2020. imec and SPTS Collaborate on Nano-TSV Processes As part of our IFTLE theme of advanced packaging and interconnect going submicron, let’s look at the imec (long renowned for both their front end and back end work) presentation “Extreme Wafer Thinning and...

The Future of Image Sensors is Chip Stacking

Sep 15, 2014

CMOS image sensors (CIS) have often been heralded as the first 3D devices in volume manufacturing. However, this is not really the case. Shellcase MVP, the first generation of CIS that used through silicon vias (TSVs) to form interconnects was still a 2D device. (Remember, TSV is not always synonymous with 3D)....

Is the Road to 3D ICs Paved with 3D SOC?

Mar 14, 2014

Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its name is 3D SoC (aka: 3D system on a chip, or 3D system partitioning, or mixed node integration – take your pick). Whatever the moniker, it looks like THIS is...

2.5D and 3D IC Technologies: Application Ready but Cost Limited?

Jan 31, 2014

Two schools of thought clearly emerged at last week’s European 3D TSV Summit, which took place on January 20 and 21, 2014 at Minatec campus in Grenoble France. One I addressed in yesterday’s post – about realizing system-level benefits – including cost – by integrating 2.5D and 3D IC technologies....

Europe in 3D

Europe in 3D: Nordson DAGE Sets Out to Measure the Invisible

Jan 15, 2014

What better place for the Queen of 3D to start out her Europe in 3D tour than a late lunch at the Crown Inn, in Colchester, Essex UK? I arrived in London on Monday afternoon, January 12, and was greeted by 3D InCites’ own Nick Richardson, business development manager (and...

Strong adhesives

Temporary Bond/Debond: Not Ready for 3D TSV Prime TIme

Dec 21, 2012

It’s too bad SUSS MicroTec’s Wilfried Bair was one of the last presenters on Friday at 3D Architecures for Systems in Packaging Symposium (3DASIP), Dec. 14, 2012, because more people should have been present to hear what he had to say. While most presenters focused on successes and future work...