Search Results

Matches for your search: "fan-out wafer level packaging "

ClassOne Technology Secures Order from Menlo Microsystems for Solstice® S8 Single-Wafer Processing System

Fast-growing microelectronics company to use industry-leading Solstice system for both electroplating and surface preparation in manufacturing of its Ideal Switch®  KALISPELL, Mont. – July 12, 2023 – ClassOne Technology, a leading global provider of advanced electroplating and wet processing tools for microelectronics manufacturing, today announced it has secured an order...

ClassOne Technology Ships Follow-on Solstice® S8 Single-Wafer Processing System to Leading Aerospace and Defense Company

ClassOne Technology, a leading global provider of advanced electroplating and wet processing tools for microelectronics manufacturing, today announced it has shipped another Solstice® CopperMax™ single-wafer processing system to a leading provider of aerospace and defense solutions. Built on ClassOne’s state-of-the-art, high-throughput Solstice platform, the system will augment the customer’s existing installed...

ACM Research Receives Multiple Purchase Orders for Ultra C wb Wet Bench Tools

Largest purchase order for wet bench systems in ACM’s history; Wet bench product line expanded to include Ultra-Low-Pressure Dry (ULD) technology FREMONT, Calif., Feb. 13, 2022 (GLOBE NEWSWIRE) — ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) applications,...

IFTLE 459: imec Develops Nano-TSV for Heterogeneous Integration

This week we continue our look at ECTC 2020. imec and SPTS Collaborate on Nano-TSV Processes As part of our IFTLE theme of advanced packaging and interconnect going submicron, let’s look at the imec (long renowned for both their front end and back end work) presentation “Extreme Wafer Thinning and...

Executive Viewpoint: Inside a Multi-Project Wafer Program for 3D Integration

Multi-project wafer (MPW) programs have long been considered an economical way to integrate different IC designs from various teams to produce IC design prototypes and low volumes. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources in this way. MPWs were historically used...

The Future of Image Sensors is Chip Stacking

CMOS image sensors (CIS) have often been heralded as the first 3D devices in volume manufacturing. However, this is not really the case. Shellcase MVP, the first generation of CIS that used through silicon vias (TSVs) to form interconnects was still a 2D device. (Remember, TSV is not always synonymous with 3D)....

Is the Road to 3D ICs Paved with 3D SOC?

Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its name is 3D SoC (aka: 3D system on a chip, or 3D system partitioning, or mixed node integration – take your pick). Whatever the moniker, it looks like THIS is...

Europe in 3D

Europe in 3D: Nordson DAGE Sets Out to Measure the Invisible

What better place for the Queen of 3D to start out her Europe in 3D tour than a late lunch at the Crown Inn, in Colchester, Essex UK? I arrived in London on Monday afternoon, January 12, and was greeted by 3D InCites’ own Nick Richardson, business development manager (and...

Strong adhesives

Temporary Bond/Debond: Not Ready for 3D TSV Prime TIme

It’s too bad SUSS MicroTec’s Wilfried Bair was one of the last presenters on Friday at 3D Architecures for Systems in Packaging Symposium (3DASIP), Dec. 14, 2012, because more people should have been present to hear what he had to say. While most presenters focused on successes and future work...