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Novel Surface Metrology Techniques for Hybrid Bonding

Executive Summary: Innovative, High Throughput Surface Metrology Hybrid bonding is enabling the next generation of advanced packaging in the semiconductor industry. As hybrid bonding occurs at the molecular level, it requires careful control of the surface topography for high yield. At Adeia, we developed new methods to improve both throughput...

Worldwide Silicon Wafer Shipments Set New Record in Q3 2022, SEMI Reports

MILPITAS, Calif. — October 25, 2022 — Worldwide silicon wafer shipments reached a new record of 3,741 million square inches (MSI) in the third quarter of 2022, increasing 1.0% quarter-over-quarter and growing 2.5% from the 3,649 MSI recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG)...

YES Receives VertaBond™ Purchase Order from a Tier 1 Memory Manufacturer

FREMONT, Calif. – Mar 15, 2021 – YES (Yield Engineering Systems, Inc.), a preferred provider of material modification and surface enhancement solutions for the semiconductor, life science and display markets, today announced that a leading memory manufacturer has ordered the YES VertaBond™ system for wafer-to-wafer and die-to-wafer bonding. The new...

EV Group: GEMINI®FB XT Automated Production Fusion Bonding System

The GEMINI®FB XT fusion wafer bonding platform features up to a 3X improvement in wafer-to-wafer bond alignment accuracy as well as a 50% increase in throughput over the previous industry benchmark platform. These performance breakthroughs clear several key hurdles to the industry’s adoption of 3D-IC/TSV technology. Testimonial According to the...

Image Courtesy of TSMC Ltd.

TSMC 2015 Technology Symposium Highlights Plans for the Coming Year

Last Tuesday, April 7, was another important day for Silicon Valley. TSMC 2015 Technology Symposium celebrated 21 years of holding this annual event to update TSMC’s loyal customers and win new ones. Rick Cassidy, President TSMC North America, opened the symposium with a long list of impressive numbers about TSMC and put them into...

My Day at the IBM Partner Summit

Want to know how to torture a journalist? Invite them to present at a conference but ask them to sign an NDA so they can’t write about it!  However, I can say this much: the 3D Program is alive and well at IBM.  From IBM Fellow, Subramanian Iyer, I learned...

C2W Bonding Approaches: Variations on Theme

As chip-to-wafer (C2W) stacking has been identified by most technologists as the best approach to 3D stacking for optimum yields and the ability to stack dies of different sizes — especially in memory/logic stacks — a number of approaches have been or are being developed by various collaboratives.  At IMAPS...