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Announcing the Winners of the 2025 3D InCites Awards

As advanced interconnect and advanced packaging processes take the helm to drive advancements in next generation semiconductor devices, innovation and collaboration across the microelectronics supply chain becomes more important than ever. So, when the 3D InCites Member Advisory Board reviewed this year’s finalists for the 2025 3D InCites Technology Enablement...

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IFTLE 603: Amkor’s Slice of the CHIPS Pie for its HVM OSAT; Samsung Texas Update

HVM OSAT In Peoria, AZ Commerce Secretary Gina M. Raimondo has identified advanced packaging as a major area of focus for the US government’s effort to rebuild American semiconductor manufacturing. The Commerce Department emphasized that developing robust advanced packaging manufacturing capacity and capability is a key priority and essential to...

IMAPS Device Packaging Conference 2025 Call for Abstracts

The 21st Annual IMAPS Device Packaging Conference (DPC 2025) will be held in Phoenix, Arizona, on March 3-6, 2025. As preparations begin for the event, IMAPS is currently accepting abstracts for technical presentations and Professional Development Courses through September 1, 2024. The 2025 IMAPS Device Packaging Conference will feature four...

IFTLE 582: SK hynix Looks at the Future of Memory Packaging for AI

At this year’s IEEE International Electron Device Meeting, [IEDM] (December in San Francisco) SK hynix gave an interesting look at “Advanced Packaging Technology in Memory Applications for Future Generative AI Era”. [Generative AI creates new content through the use of machine learning models such as generative adversarial networks. Such frameworks...

advanced packaging model

Will a New Advanced Packaging Foundry Model Extend Moore’s Law?

Challenges to 3DHI and chiplets remain, but new advanced packaging foundry solutions are stacking up The industry consensus is that the path to extending Moore’s Law lies in heterogeneous integration (HI) and chiplet architectures. Why, then, are we still waiting for the full adoption of HI, 3DHI, and chiplets? The...

Community Member Monthly Highlights – April 2023

Cadence, ASE Group, and Chung Yuan Christian University (CYCU) announced collaboration on an education and training program to cultivate talent for 3D-IC Design. Cadence collaborates with universities on system packaging education and talent development through the Cadence Academic Network program, which provides students with access to Cadence advanced IC packaging...

Plan Optik and 4JET Jointly Develop New Process for Advanced Packaging

• Process innovation for through-glass vias in the field of advanced packaging • Premiere at Touch Taiwan on April 19-21 in Taipei Plan Optik AG (Elsoff, Germany) and 4JET microtech (Alsdorf, Germany) have jointly developed a process chain for the highly productive production of metallized through-glass vias. The new VLIS...

Interconnect Reliability: From the Chip to the System

Interconnect reliability is critical to the reliability of semiconductor packaging and electronic systems. If we look at the life cycle from the chip to the system—from IC design, wafer fab, and packaging, to board assembly and system integration—the common element is the “interconnect thread” for the reliability of the electronic...

Triton Microtechnologies Receives Funding to Ramp Glass Interposer Manufacturing for 3D and 2.5D Semiconductor Packaging

Start-up Triton Microtechnologies, a designer and manufacturer of ultra-thin glass interposer technology that enables advanced semiconductor-packaging solutions, has met six-month production milestones that have triggered an additional $3.2M in funding from parent companies Asahi Glass Co., Ltd. (AGC) of Tokyo and nMode Solutions Inc. in Oro Valley, Arizona. Triton will...