Search Results

Matches for your search: "fan-out wafer level packaging "

The Growing Importance of Advanced Packaging in Europe – Recap of ERS TechTalk

Mar 24, 2025

Advanced packaging has emerged as a critical enabler of next-generation applications for artificial intelligence (AI), high-performance computing, wearables, 6G communication, and defense technologies. As traditional scaling approaches face increasing limitations, Advanced packaging enables further miniaturization and improved performance through heterogeneous integration, chip stacking, and high-density interconnects. In Europe, advanced packaging...

February Member News: Expansion, Collaborations, and Events Galore

Feb 27, 2025

February member news shows dynamic activity for semiconductor industry, with exciting advancements in technology, strategic expansions, key industry events, and notable leadership updates. From breakthrough product launches and major acquisitions to industry collaborations, here’s a look at what our members achieved this month. Technology Innovation and Product Developments Nordson Electronics...

EV Group and Fraunhofer IZM-ASSID personnel next to an EVG®850 DB fully automated UV laser debonding and cleaning system installed in Fraunhofer’s newly established Center for Advanced CMOS and Heterointegration Saxony (CEASAX) in Dresden, Germany. From left to right: Gerald Silberer, Regional Sales Director Europe (EV Group); Dr. Andreas Gang, Group Leader Pre-Assembly / Wafer Bonding (Fraunhofer IZM-ASSID); Dr. Manuela Junghähnel, Site Manager (Fraunhofer IZM-ASSID); Markus Wimplinger, Corporate Technology Development & IP Director (EV Group); Andreas Pichler, Regional Sales Manager Europe (EV Group); Robert Wendling, Technical Assistant Wafer Bonding (Fraunhofer IZM-ASSID); and Dr. Frank Windrich, Deputy Site Manager (Fraunhofer IZM-ASSID). © Fraunhofer IZM / Silvia Wolf.

EV Group and Fraunhofer IZM-ASSID Expand Partnership in Wafer Bonding for Quantum Computing Applications

Jun 13, 2024

EV Group and Fraunhofer IZM-ASSID partnership kicks off with the installation of EVG850 automated laser debonding system at the newly launched Center for Advanced CMOS and Heterointegration Saxony (CEASAX) EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and Fraunhofer...

ECTC 2024 3D InCites Community Member Preview

May 13, 2024

2024 is a big year for 3D InCites members at the Electronic Components and Technology Conference (ECTC). With 34 of our community member companies presenting, exhibiting, and in some cases both, this may be our most well-represented year yet! ECTC 2024 is packed with program sessions, interactive presentations, and special...

IFTLE 541: Predicted Locations for CHIPS Innovation Hubs; Skywater/BRIDG IBAS Funding

Nov 28, 2022

CHIPS Act Innovation Hubs SEMI has published an interesting article where they predict 10 likely locations for CHIPS Act Innovation Hubs. Aside from the CHIPS Acts $52B in subsidies for American chipmakers and 25% tax credits for capital expenditures, the Department of Commerce is also allocating $10B (over five years)...

IFTLE 532: Fraunhofer IZM Examines Panel Level Processing Technology Limits

Sep 06, 2022

Continuing our look at presentations at the 2022 ECTC, who better to examine the question “Panel Level Packaging – Where are the Technology Limits?” than Tanja Braun and the group at IZM Fraunhofer who have become experts in this processing area over the last several years? Although they do not...

Part 2: IMAPS DPC 2017 Covers Range of High-tech Topics, including EDA

Apr 18, 2017

The keynotes outlined in Part 1 of IMAPS DPC 2017 Covers Range of High-tech Topics, including EDA were obviously very important, but a relatively small part of the entire conference. After the two keynotes on Tuesday morning, I listened to YOLE’s presentation, delivered by Santosh Kumar, and learned that the...

IWLPC 2016 Keynotes Look to A Connected Future Enabled by Advanced Packaging

Nov 04, 2016

The 2016 International Wafer-Level Packaging Conference (IWLPC), which took place October 18-20, 2016 in San Jose, CA, focused on a theme of “Bridging the Interconnect Gap”, as the industry faces new challenges due to the onslaught of Big Data brought about by the Internet of Things (IoT). To provide vision...

Panel-level Packaging: the High Volume Manufacturing Roadmap has Yet to be Built

Feb 09, 2016

Over the past few years, it becomes clear that some panel-level packaging choices will be more suitable than others for successful commercial development. So, when will the panel-level packaging industry take off? How will it evolve? “At Yole, we’ve identified five key packaging platforms that can be processed on a...

European 3D Summit: Putting 3D Packaging To Work

Jan 31, 2016

Now that we’ve determined that advanced wafer level packaging — including embedded technologies, fan-out wafer level packaging, and 3D packaging — add value to the devices in which they are implemented, the next step is understanding which option offers the best cost/performance ratio for specific product applications. One of the...