Search Results

Matches for your search: "fan-out wafer level packaging "

What to Know Before Buying an IMAPS Academy Course

If you’re new to the advanced packaging industry, it may have crossed your mind to invest in a professional development course. IMAPS, or the International Microelectronics Assembly and Packaging Society, offers exactly that. Their packaging-specific, IMAPS Academy courses are aimed at promoting a stronger understanding of key parts of the...

Electronics Packaging – From Afterthought to Product Differentiator

Electronics Packaging vs. Advanced Packaging Electronics packaging is generally divided into three major areas, traditional packaging – also called standard or mainstream packaging, and sometimes even just “Others”: advanced packaging and emerging packaging technologies. Traditional packaging is everything with wire or ribbon bond interconnects on a ceramic, metal lead frame,...

ERS electronic GmbH Takes the Lead in Fan-Out Panel Level Packaging Equipment Manufacturing

ERS electronic GmbH, the innovation leader in thermal management solutions for the semiconductor manufacturing industry, is taking the first ever step towards developing the new generation of thermal debonding and warpage adjustment tools for fan-out panel level packaging (FOPLP). The new ERS MPDM700 supports the increasing demand for fast prototyping...

Impressions from ECTC 2017

Let’s start with the indoor rainstorm. I arrived at the Swan and Dolphin in Orlando just in time for the fan-out plenary session of ECTC 2017, so tossed my stuff in my room and headed on in (wearing jeans, no less!) You can read about that here. Afterward, I had...

FOPLP

Fifty Shades of Fan-out Discussed at ECTC 2017

The fan-out conversation that started at IMAPS DPC 2017 in March continued this week at the annual Electronics Components Technology Conference (ECTC), which took place in Orlando at the Walt Disney World Swan and Dolphin Resort. The buzz started during the Tuesday evening plenary session, where panelists Douglas Yu, TSMC,...

IWLPC 2016 Keynotes Look to A Connected Future Enabled by Advanced Packaging

The 2016 International Wafer-Level Packaging Conference (IWLPC), which took place October 18-20, 2016 in San Jose, CA, focused on a theme of “Bridging the Interconnect Gap”, as the industry faces new challenges due to the onslaught of Big Data brought about by the Internet of Things (IoT). To provide vision...

Panel-level Packaging: a Promising Market

 For many years now, the semiconductor industry development has been governed by  Moore’s law and the increasing demand for higher performance and lower manufacturing costs. Under this context, the “More than Moore” company, Yole Développement (Yole) has identified a strong interest for panel-level packaging technologies. “At Yole, we saw a...

Semiconductor Supplier Updates from SEMICON West 2015

No SEMICON West would be complete without a few laps around Moscone North and South, and some one-on-one chats with suppliers. I stopped in to see several semiconductor supplier companies who annually request an audience with the Queen of 3D to talk about their latest accomplishments, as well as gain...

Wafer Level Packaging and Stacking take Center Stage at Asia Conferences

I thought I would go to Singapore, attend EPTC (Electronic Packaging Technology Conference 2013) and then take off on my personal vacation to India to attend my 40th high school reunion and 35th college reunion – two weeks tops. It escalated quickly. It ended up being 34 day, 20 city,...