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EMIB

Cadence and Intel Foundry Collaborate to Enable Heterogeneous Integration with EMIB Packaging Technology

Feb 27, 2024

Cadence and Intel Foundry have collaborated to develop and certify an integrated advanced packaging flow utilizing Embedded Multi-die Interconnect Bridge (EMIB) technology to address the growing complexity in heterogeneously integrated multi-chip(let) architectures. The collaboration enables Intel customers to leverage advanced packaging to accelerate the high-performance computing (HPC), AI, and mobile...

Glass Carrier for GaAs Wafer Processing

May 19, 2022

Gallium arsenide (GaAs) is used in the manufacture of devices such as microwave frequency integrated circuits, monolithic microwave integrated circuits, infrared light-emitting diodes, laser diodes, solar cells, and optical windows. Handling and processing thin GaAs wafers is usually enabled by using a sapphire wafer as a carrier, which is expensive...

IFTLE 475: EPTC 2020: IME on Hybrid Bonding Challenges; Latest on Intel

Feb 01, 2021

IME – Hybrid Bonding Studies Singapore’s Institute of Microelectronics – IME / AStar – was certainly the most prolific presenter at the conference. In their presentation, “Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies”, they review in great detail processing issues prevalent in hybrid bonding. Wafer-level fine-pitch hybrid bonding, first...

How to Create a Vibrant Semiconductor Manufacturing Industry in the United States

Jul 13, 2020

Having spent the last 30 years working in semiconductor manufacturing, it is both exciting and unsettling to see renewed political interest in the revitalization of this industry in the United States. Gone are the days of ‘It doesn’t make any difference whether a country makes computer chips or potato chips!’...

ECTC 2015 Supplier Update

Jun 10, 2015

While Herb Reiter dove deep into the technology sessions at ECTC 2015, I spent most of my time picking the brains of suppliers who have introduced products targeting advanced wafer level packaging and 3D ICs. Overall, I’ve noticed efforts are becoming really targeted, and are focused on remaining challenges like thermal management, improving...

French Institutes IRT Nanoelec and CMP Team up to Offer World’s First Service for Post-process 3D Technologies on Multi-Project-Wafer

Mar 10, 2015

GRENOBLE, France – March 5, 2015 – IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW). The new and disruptive 3D configurations and assemblies created by...

NEXX Systems Joins Tokyo Electron (TEL) as a Wholly Owned Subsidiary

Mar 16, 2012

Tokyo Electron Limited announced the completion of a definitive acquisition agreement with NEXX Systems Inc. Over the years, NEXX collaborated with TEL to study process technology in advanced packaging equipment for the development of 3D Thru Silicon Vias (TSV), giving both companies an opportunity to work together and setting the...

SEMATECH Reports Advances in Bond Process for 3D Integration Development

Sep 03, 2011

With a focus on providing cost-effective and reliable solutions to accelerate manufacturing readiness of 3D technology options, SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual Device Packaging Conference (DPC) on March 7-10 in Scottsdale, AZ. Technologists from SEMATECH’s 3D Interconnect program have demonstrated a novel die-to-wafer...

Soitec Unleashes the Power of Three

Feb 11, 2009

A walk across the impressive Bernin, France campus that is home to two of Soitec Group’s three divisions takes you past three production-level fab facilities – aptly named Bernin 1, Bernin 2, and Bernin 3, plus a development facility. The company’s three-stage business model encompasses innovation, licensing, and production...