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As summer holidays came to a close, September found our member companies ramping up new products and opening new facilities. The industry event season kicked off with SEMICON Taiwan and SEMICON India, IEEE 3DIC, MEMS & Imaging Sensors Summit, and more, and our members actively participated. Many of them were...
Customers and collaborators will have early access to next-generation glass substrate tools and software solutions to accelerate panel-level packaging R&D Onto Innovation Inc. today announced the opening of the company’s Packaging Applications Center of Excellence (PACE), a first-of-its-kind facility in the U.S. dedicated to panel-level packaging (PLP) innovations enabling 2.5D...
Bridging the gap: innovations in chiplet interconnect technology Chiplet interconnects begin with small chips – or chiplets – with a well-defined function that can be incorporated with other chiplets into a single package or system Dense interconnections between chiplets ensure fast, high-bandwidth electrical connections. This article discusses both interposer and...
Let’s continue our look at papers presented during October’s IPC Advanced Packaging Symposium: “Building the IC-Substrate and Package Assembly Ecosystem”. NIST and the US CHIPS Act As we all know by now, the CHIPS and Science Act is being managed by NIST under the Dept of Commerce. NIST has always...
As the semiconductor packaging technology evolves in the “More than Moore” era, many advanced processes have presented challenges in manufacturing. Often, challenges in precision die bonding, for example, have led to trade-offs in yield, throughput, and ultimately manufacturing cost. Precision alignment has become one of the key capabilities for several...
2020 proved to us that our world is wholly unpredictable. As the year began with optimism for a new decade and excitement for what the new decade might bring, the last thing expected was the arrival of COVID-19. Within a short time, the pandemic created unprecedented disruption while shattering lives...
In 1994 TSMC, a small wafer foundry from Taiwan held its first Technology Symposium. Since 1999 I have had the privilege to work with TSMC and closely follow their success in building a powerful and cost-effective ecosystem for the fabless IC vendors and foundry business model. To measure their success...
It’s been a busy few weeks for me as I attended both the International Wafer Level Packaging Conference (IWLPC), October 24-26, 2017 at the DoubleTree in San Jose and SEMI-MSIG’s MEMS and Sensors Executive Congress, October 31-Nov. 2, at the Hayes Mansion in San Jose. In addition to taking in...
On March 15, 2017, TSMC held its 23rd Symposium, based on popular request, at the Santa Clara Convention Center. I had the opportunity to attend the entire symposium and want to share some of my impressions and facts learned with you. TSMC, by far the biggest pure-play foundry, has pioneered...
For me, SEMICON West involves a careful balance of attending sessions, keynotes and panels, combined with one-on-one interviews with thought leaders in 3D ICs, as well as manufacturing suppliers who have the onerous task of developing, promoting, and selling the next great solution for 2.5D and 3D IC manufacturing. Over...
