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Bridging the gap: innovations in chiplet interconnect technology Chiplet interconnects begin with small chips – or chiplets – with a well-defined function that can be incorporated with other chiplets into a single package or system Dense interconnections between chiplets ensure fast, high-bandwidth electrical connections. This article discusses both interposer and...
This interview with Trymax Semiconductor’s Peter Dijkstra, Chief Commercial Officer (CCO), and Karsten Arts, Process Engineer first appeared in Atomic Limits as part of a series of posts about companies within the atomic scale processing industry. The goal of the series was to provide information about the kind of products...
Preparation for the 73rd ECTC started one year ago and was strongly supported by over 250 experts from 15 countries, members of 10 technical committees. The technical committees critically reviewed 618 submitted abstracts from industry (56.1%) and academia (43.9%), resulting in 369 technical papers. The papers, organized in 41 sessions,...
Let’s continue our look at papers presented during October’s IPC Advanced Packaging Symposium: “Building the IC-Substrate and Package Assembly Ecosystem”. NIST and the US CHIPS Act As we all know by now, the CHIPS and Science Act is being managed by NIST under the Dept of Commerce. NIST has always...
2020 proved to us that our world is wholly unpredictable. As the year began with optimism for a new decade and excitement for what the new decade might bring, the last thing expected was the arrival of COVID-19. Within a short time, the pandemic created unprecedented disruption while shattering lives...
I was halfway through my post about my day at Virtual SEMICON Taiwan, when I realized that to do the Global SiP Summit justice, meant it would need its very own post. The live version of the event spanned three full days. That’s a lot of content. While the on-demand...
In 1994 TSMC, a small wafer foundry from Taiwan held its first Technology Symposium. Since 1999 I have had the privilege to work with TSMC and closely follow their success in building a powerful and cost-effective ecosystem for the fabless IC vendors and foundry business model. To measure their success...
It’s been a busy few weeks for me as I attended both the International Wafer Level Packaging Conference (IWLPC), October 24-26, 2017 at the DoubleTree in San Jose and SEMI-MSIG’s MEMS and Sensors Executive Congress, October 31-Nov. 2, at the Hayes Mansion in San Jose. In addition to taking in...
A little over a year ago, I wrote a Knowledge Portal entry about the cost of 3D ICs. Here I am again to tackle the issue of 2.5D and 3D cost reduction from a slightly different angle. This entry is based on what SavanSys presented at IMAPS Device Packaging 2016....
For me, SEMICON West involves a careful balance of attending sessions, keynotes and panels, combined with one-on-one interviews with thought leaders in 3D ICs, as well as manufacturing suppliers who have the onerous task of developing, promoting, and selling the next great solution for 2.5D and 3D IC manufacturing. Over...
