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Every metal layer on a wafer, from M1 at the front end to redistribution for wafer-level packaging (WLP), requires patterning. Selective material removal, including etching oxides and metals, often becomes the critical path. It is essential to thoroughly strip photoresist and minimize contamination to achieve the desired yield. Plasma etching...
Company broadens portfolio to include next-generation substrates and panel-level processes for heterogeneous semiconductor solutions FREMONT, Calif., Nov. 15, 2022 – Lam Research Corp. (Nasdaq: LRCX) today announced that it has completed the acquisition of SEMSYSCO GmbH, a global provider of wet processing semiconductor equipment from Gruenwald Equity and other investors. With the...
Wafer-level packaging (WLP) saw significant growth in 2021 due in large part to the increased performance needs of data-driven 5G network devices. Because WLP is performed when chips are still on the wafer, ACM Research has been able to leverage and adapt our expertise in front-end solutions to address high-volume...
3D InCites presented the 2019 process of the year award to Eric Beyne and Arnita Podpod of IMEC for their flip-chip on fan-out wafer-level package (FC on FOWLP) process that avoids the use of TSVs in active chips to achieve high-density packaging. Advanced packaging practitioners may have noticed the similarities...
IIFTLE is always on the lookout for technologies that will require advanced packaging solutions. Fingerprint sensors for today’s latest smartphones appear to be one of those applications. Packaging for Fingerprint Sensors DIGITIMes recently reported that the manufacture of under-display optical fingerprint sensors for use in 5G-enabled phones will require extensive...
While the shopping malls and specialty stores in and around San Francisco were packed with people hunting for Holiday presents, a very dedicated crowd of 3D IC developers and users from all over the world got together near San Francisco, for the 12th 3D ASIP conference, which featured, once again,...
There is no rest for the weary. Just because we can finally declare that 3D ICs are in production doesn’t mean we’re done working on it. To the contrary, efforts are ongoing at research institutes like imec in Belgium and Leti in France to take 3D integration to the next...
As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package architectures has become key to enable the integration of greater amounts of chip functionality in smaller form factors. This need for form factor reduction, together with smaller process geometries and...
STATS ChipPAC Ltd, and outsourced semiconductor assembly and test (OSAT) provider, announced it is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities. STATS ChipPAC was one of the first OSATS to invest in TSV technology with a 51,000 square foot research and development...
It’s a good story that’s been 30 years in the making. From its founding by Erich and Aya Maria Thallner in 1980 and subsequent launch of the world’s first double-sided mask aligner for the emerging MEMS market five years later; to its most recent industry-first launch of a fully-automated wafer...
