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LQDX and Arizona State University Sign Semiconductor Packaging Collaboration Agreement

LQDX Inc., developer of high-performance materials and process IP for advanced semiconductor packaging,  announced that it has signed a formal agreement with Arizona State University (ASU) to further its partnership which began in 2024, focused on advanced IC-substrates, fan out wafer level packaging (FOWLP) and glass core metallization, as enabled...

IFTLE 611: Amkor Clarifies Arizona Facility Activity

Wolfspeed & Hemlock Semiconductor Get Their CHIPS Act Share Arizona Facility to Focus on High Performance Computing In IFTLE 577 we reported that Amkor had announced plans to build an advanced packaging and test facility in Peoria, Arizona. In IFTLE 603 we reported that Amkor Technology had signed a preliminary...

When Plasma Matters: Three Reasons to Choose Plasma

Every metal layer on a wafer, from M1 at the front end to redistribution for wafer-level packaging (WLP), requires patterning. Selective material removal, including etching oxides and metals, often becomes the critical path. It is essential to thoroughly strip photoresist and minimize contamination to achieve the desired yield. Plasma etching...

A Retrospective: A Successful 9th ESTC 2022

The Electronics System-Integration Technology Conference (ESTC) is the premier international event in the field of electronics packaging and system integration in Europe. The conference takes place every two years and is the IEEE EPS flagship conference in Europe, organized by IEEE EPS Region 8 (EMEA) Chapter in association with IMAPS...

Lam Research Acquires SEMSYSCO to Advance Chip Packaging 

Company broadens portfolio to include next-generation substrates and panel-level processes for heterogeneous semiconductor solutions   FREMONT, Calif., Nov. 15, 2022 – Lam Research Corp. (Nasdaq: LRCX) today announced that it has completed the acquisition of SEMSYSCO GmbH, a global provider of wet processing semiconductor equipment from Gruenwald Equity and other investors. With the...

ASE Introduces VIPack™ to Help Transform Packaging Solution Enablement

SUNNYVALE, Calif., June 1st, 2022 –Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE:ASX, TAIEX: 3711), today introduced VIPack™, an advanced packaging platform designed to enable vertically integrated package solutions.  VIPack™ represents ASE’s next generation of 3D heterogeneous integration architecture that extends design rules and...

IFTLE 506: Tyndall Packaging for Integrated Photonics; TSMC/Sony Joint Venture

Continuing our look at the 2021 IMAPS International Symposium, let’s take a deeper look at the integrated photonics keynote presentation by Tyndall Institute. Integrated Photonics at Tyndall Institute Peter O’Brien discussed “Packaging Technologies for Integrated Photonics”. Tyndall Institute is part of Univ College Cork Ireland. They offer prototyping platforms and...

EV Group Addresses Key Process Gap in Heterogeneous Integration with Collective Die-to-Wafer Hybrid and Fusion Bonding Demonstration

EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has successfully demonstrated a complete process flow for collective die-to-wafer (D2W) hybrid and fusion bonding with sub-two-micron placement accuracy utilizing existing EVG wafer bonding technology and processes,...

SUSS MicroTec Launches XB8 – a New Semi-Automated High-Force Wafer Bonder

Garching, September 17, 2015 – SUSS MicroTec, a global supplier of equipment and applications for the semiconductor industry and related markets, has launched the new bonding platform XB8 today. The XB8 wafer bonder is designed for a wide range of bonding processes. It supports substrates with a wafer size of...

Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress

As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package architectures has become key to enable the integration of greater amounts of chip functionality in smaller form factors. This need for form factor reduction, together with smaller process geometries and...