Search Results

Matches for your search: "fan-out wafer level packaging "

Figure 3: High-speed wafer transfer via the Trymax equipment front-end module.

When Plasma Matters: Three Reasons to Choose Plasma

Every metal layer on a wafer, from M1 at the front end to redistribution for wafer-level packaging (WLP), requires patterning. Selective material removal, including etching oxides and metals, often becomes the critical path. It is essential to thoroughly strip photoresist and minimize contamination to achieve the desired yield. Plasma etching...

Amkor Advanced Packaging Enables the Car of the Future

TEMPE, Ariz.–Jun. 13, 2023– Amkor Technology, Inc. (Nasdaq: AMKR), a leading provider of semiconductor packaging and test services and the #1 automotive OSAT, is innovating advanced packaging to enable the car of the future. The evolution of the enhanced automotive experience has been dramatic over the past few years—a rise...

Lam Research Acquires SEMSYSCO to Advance Chip Packaging 

Company broadens portfolio to include next-generation substrates and panel-level processes for heterogeneous semiconductor solutions   FREMONT, Calif., Nov. 15, 2022 – Lam Research Corp. (Nasdaq: LRCX) today announced that it has completed the acquisition of SEMSYSCO GmbH, a global provider of wet processing semiconductor equipment from Gruenwald Equity and other investors. With the...

ASE Introduces VIPack™ to Help Transform Packaging Solution Enablement

SUNNYVALE, Calif., June 1st, 2022 –Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE:ASX, TAIEX: 3711), today introduced VIPack™, an advanced packaging platform designed to enable vertically integrated package solutions.  VIPack™ represents ASE’s next generation of 3D heterogeneous integration architecture that extends design rules and...

Update on the Heterogenous Roadmap and the CHIPs Act

Years ago, when I was just a young pup in the industry, my manager asked me to attend a meeting in San Jose, California in 1997, where I participated in helping to define one of the early road maps for semiconductor technology, The early version I participated in was sponsored...

IFTLE 506: Tyndall Packaging for Integrated Photonics; TSMC/Sony Joint Venture

Continuing our look at the 2021 IMAPS International Symposium, let’s take a deeper look at the integrated photonics keynote presentation by Tyndall Institute. Integrated Photonics at Tyndall Institute Peter O’Brien discussed “Packaging Technologies for Integrated Photonics”. Tyndall Institute is part of Univ College Cork Ireland. They offer prototyping platforms and...

EV Group Addresses Key Process Gap in Heterogeneous Integration with Collective Die-to-Wafer Hybrid and Fusion Bonding Demonstration

EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has successfully demonstrated a complete process flow for collective die-to-wafer (D2W) hybrid and fusion bonding with sub-two-micron placement accuracy utilizing existing EVG wafer bonding technology and processes,...

SUSS MicroTec Launches XB8 – a New Semi-Automated High-Force Wafer Bonder

Garching, September 17, 2015 – SUSS MicroTec, a global supplier of equipment and applications for the semiconductor industry and related markets, has launched the new bonding platform XB8 today. The XB8 wafer bonder is designed for a wide range of bonding processes. It supports substrates with a wafer size of...

Notes from the FOA Packaging and Test Group

The Packaging and Test Group of the Fab Owners Association, (Cupertino, CA) held its first official meeting on February 4th. This was just one of the meetings held as part of the third annual FOA Collaborative Forum in Santa Clara, CA. The fourteen inaugural FOA packaging and test group (FOA-PT) members heard...

Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress

As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package architectures has become key to enable the integration of greater amounts of chip functionality in smaller form factors. This need for form factor reduction, together with smaller process geometries and...