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As IFTLE has explained previously, Investments in semiconductors will not succeed without investments in advanced packaging. The CHIPS for America program, agreeing with this premise, has announced that it will support the development of advanced packaging technology in the United States that can be transferred to manufacturing facilities, including recipients...
John Park, product management group director, of Custom IC & PCB Group at Cadence, is a go-to authority on advanced packaging, as I learned as he and I talked about the world of 3D ICs or 3D Heterogeneous Integration (3DHI). His extensive background in packaging, not chips, was fortified early...
Wafer Thinning and Nano TSVs In the last few years, Ann Jourdain of IMEC and co-workers have described silicon device stacking through extreme silicon thinning technology. Recently Jourdan and Dave Thomas of SPTS reviewed this technology for the Jan/Feb issue of Chip Scale Review. The technology is interesting enough that...
In recent blogs, we have discussed the damage done to Intel’s leading-edge technology reputation by major delays in both their 10nm and 7nm product introductions [ see IFTLE 458]. We have also seen them try to put a positive spin on the fact that they may have to go external...
Wilmington, Mass. (12/11/2018)—Rudolph Technologies, Inc. (NYSE: RTEC) today announced the receipt of over $12M in new orders for its recently-released NovusEdge™ system for edge and backside inspection on bare silicon wafers. The new orders are for capacity expansions at our existing customers as well as orders from two additional large wafer manufacturers...
EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the all-new BONDSCALE™ automated production fusion bonding system. BONDSCALE is designed to fulfill a wide range of fusion/molecular wafer bonding applications, including engineered substrate manufacturing and 3D integration approaches...
Through silicon via (TSV) reveal is a critical part of the wafer-thinning step in 3D IC backside processing, where the wafer is thinned to expose the Cu “nails” that ultimately form the interconnect between die stacks. Some of the risks involved in this step include backside contamination (Cu diffusion) due...
49 years ago, Solid State Equipment, LLC (SSEC) opened its doors with its first piece of semiconductor equipment; a seam sealer for welding the lid on hermetic packages. Today, that tool still exists, and although it now accounts for 1% of SSEC’s revenue instead of 50%, sales have remained constant...
Generation Mobile, “Thin is In” and More Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function. To address these massive changes, SEMICON West will feature a number of programs on new packaging technologies and processes with speakers...
Company to share key developments and highlights at SEMICON West
