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Artificial Intelligence is Driving Panel Level Packaging

TSMC has announced a roadmap to 9 reticle packages to meet the demand for large scale systems in a package. (A multi-reticle package has more than 800mm2 area of chips in the package.) Nvidia’s Blackwell currently has two chips slightly larger than 800mm2 in the package with eight stacks of...

SEMICON West 2024

SEMICON West 2024 “Stronger Together” Member Preview

SEMICON West 2024 is themed Stronger Together. SEMI’s message of the year is focused on the need for global collaboration and it carries through to this flagship event. From July 8-11, 2024.  Join us in San Francisco at the Moscone Center for insights into semiconductor industry market trends and to...

A Career in Microelectronics Through the Eyes of Bill Chen

The semiconductor and microelectronics industries are in the midst of a workforce crisis created by, among other things, the combination of explosive growth and a maturing workforce. Competition for STEM talent in other industries has made it difficult to recruit the latest generation of graduates, who are lured by seemingly...

IFTLE 464: TSMC’s Family of Packaging Technologies Create 3D Fabric

TSMC recently held its 26th annual Technology Symposium, so let’s take a look at the highlights of their presentations focusing on their advanced packaging activities featuring a new concept called 3D fabric. But first, among the front-end highlights were the following: Scaling from the N7 to N5 to N3 process...

IFTLE 449: Advanced Packaging and Chiplets at the IMAPS DPC

ECTC Meeting Goes Virtual For those that have not seen the announcement, the Electronics Component Technology Conference (ECTC) held annually the first week of June has been canceled. At the time of this writing, they are trying to assemble video presentations from the submissions and have a virtual conference. We’ll...

3D InCites Community Members to Play Key Role at IMAPS DPC

What’s on the agenda for the 2020 IMAPS Device Packaging Conference (DPC)? So much, and too much to share it all. Our 3D InCites Community members and sponsors are playing key roles… Booth 56: StratEdge Corporation StratEdge Corporation, a leader in the design, production, and assembly of high-frequency and high-power...

EPS 2019: Imagining Thomas Edison as the Father of Advanced Packaging

Thomas Alva Edison didn’t invent semiconductor device packaging, but he might have, had he lived just one more generation. “I find out what the world needs. Then I go ahead and try to invent it.”* Edison passed away in 1931, less than twenty years before John Bardeen, Walter Brattain, and...

Executive Viewpoint: The Impact of Process Control on FOWLP and 3D IC

As Si interposer and 3D stacked memory devices enter into production, albeit in low volumes, semiconductor manufacturers are lining up their ducks to be ready for high volume manufacturing (HVM) when it happens. As a result, some suppliers of high volume manufacturing equipment who have been rather quiet through the...

IMAPS 2014: The Future of Packaging is System Integration

The annual International Microelectronics and Packaging Society (IMAPS) International Symposium has always focused more on advancements in mainstream packaging technologies, and left the emerging innovative processes to its spring event, the International Device Packaging Conference. As such, its speakers generally offered the most conservative viewpoints on 3D adoption. In a...

Trends and challenges for thin wafer processing

Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are vital to a multitude of semiconductor applications such as MEMS, compound semiconductors, LEDs, fan-out WLP, CMOS image sensors (CIS) and most recently, 3D IC using TSV interconnects.