Search Results

Matches for your search: "fan-out wafer level packaging "

3D InCites Community Member Monthly Highlights — June

Our 3D InCites Community Members had an abundant amount of news to share this month, so we thought we should do a quick recap in our June edition of monthly highlights. If you have news to share, please don’t forget to share it with your 3D InCites team! ASE announced...

Why An Internship in Fan-out Technology Was My Dream Come True

I joined ERS electronic GmbH for an internship in fan-out technology from October 2020 to June 2021 as a mandatory part of my Master’s degree in Mobile and Embedded Systems at the University of Passau. My internship at ERS gave me great exposure to the inner workings of the semiconductor...

IFTLE 456: SPIL Fan-out Embedded Bridge (FOEB) Technology

in this week’s post, we continue our look at the 2020 IEEE ECTC virtual conference. Siliconware’s presentation “Scalable Chiplet Package Using Fan-out Embedded Bridge (FOEB)” focused on the advantages of its FOEB package for the server, high-performance computing, router, and switcher markets.  The difference between today’s 2.5D and FOEB is...

EV Group Establishes Heterogeneous Integration Competence Center

New HI Competence Center to help customers accelerate new product development fueled by heterogeneous integration and advanced packaging EV Group (EVG) today announced that it has established the Heterogeneous Integration Competence Center™, which is designed to assist customers in leveraging EVG’s process solutions and expertise to enable new and enhanced...

Weathering the Storm and Positioning the Semiconductor Industry for Growth

2019 has been a sobering year for the semiconductor industry. It started out with such high hopes, coming off of a banner year in 2018, during which we hit some significant milestones. Now we find ourselves in the midst of the worst downturn since 2008, minus the global financial crisis,...

System Plus Consulting confirms: Apple A10 processor uses TSMC’s inFO technology

System Plus Consulting announces the release in the next few weeks of a complete report on TSMC’s Integrated Fan-Out (inFO) technology used for Apple’s A10® processor packaging. And few results are already available. Indeed System Plus Consulting’s experts propose you to discover a previous of the first conclusions. Featured in the latest...

Advanced Packaging and 3D come to MRS Spring Meeting

For the first time ever, the Materials Research Society (MRS) brought its annual Spring meeting to Phoenix. I have never attended this event, as it is deeply academic, and has not been on my radar for 3D or advanced packaging technologies. However, after finding out from fellow SemiSisters, Rozalia Beica,...

EMIB, the 3D Technology Landscape, and other Keynote Moments from IMAPS DPC 2016

This year’s keynote talks at the 2016 IMAPS Device Packaging Conference (DPC 2016) provided some new insight into a number of interesting areas of importance to the advanced packaging community. I already addressed Bill Chen’s talk, which focused on system-in-package (SiP) and introduced a 3D Fan-out SiP approach. Here, I’ll...

IC Packaging: An Essential Enabler and Differentiator, Part 1

The Great Miniaturization … SEMI/MEPTEC Conference Nov 10 & 11 After 50 years of following Moore’s Law and reaping major benefits with every feature size reduction, the economics of transistor scaling are now no longer universally applicable. Only designs that can be sold in extremely high volumes are likely to...

Hey Intel, get your own buzzword…

So there I was, listening to Eric Beyne talk about the importance of co-developing advanced CMOS and 3D ICs because one directly affects the other, when my thoughts turned to once again to FinFets (is this what he means by advanced CMOS?) I wondered whether these so-called 3D transistor structures...