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IFTLE 608: Is Chip Packaging the New Front on the US-China CHIP WARS?

US-China CHIP WARS Now Encompass Advanced Packaging In the Aug 21st issue of Asia Times, Scott Foster wrote an interesting article entitled “Advanced IC Packaging is Next Front in the Chip Wars”; certainly something we all see happening. Certainly, IFTLE agrees that advanced IC packaging is the new source of...

Hybrid Bonding takes Heterogeneous Integration to the Next Level

Hybrid bonding enables an assortment of possible chip architectures, mainly targeted at high-end applications including high-performance computing (HPC), artificial intelligence (AI), servers, and data centers. As the technology matures, further growth is projected into consumer applications, memory devices including high bandwidth memory (HBM), and mobile and automotive applications that could...

IFTLE 428: Panel Level Processing: We’ve Come A Long Way Baby!

It was in 1992 when Ted Tessier and I, in our paper, “Overview of MCM Technologies: MCM-D”, at the IMAPS Symposium in San Francisco, drew the analogy to the evolving LCD industry. “The LCD industry had spawned the development of a whole new class of large format, high-throughput thin-film processing...

Advanced Substrates; Key Enabler of Future Advanced Packaging Solutions

“Advanced substrates are the key interconnect component of advanced packaging architectures,” comments Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole Développement (Yole). Indeed advanced substrates are critical in enabling future products and markets. To answer to technology evolution and market needs, Yole’s advanced packaging team...

3D ASIP 2015: 3D Manufacturing Processes from the Early Days to the Present

For the first time since the 3D Architectures for Semiconductor Integration and Packaging (3DASIP) Conference was established, the organizing committee decided to acknowledge the work of two researchers who were instrumental in developing the core processes that enabled 3D TSV development. In a brief ceremony, Dr. Phil Garrou presented 3DIC Pioneer...

SUSS MicroTec: A 3D Approach


EV Group Adds In-Line Metrology Capability to Wafer Bonding Systems to Support High-Volume 3D-IC and TSV Manufacturing

First-ever Integration of In-line Metrology with Temporary Bonding/Debonding Enables More Repeatable and Reliable Process, Improved Yields and Lower Cost of Production ST. FLORIAN, Austria, June 21, 2011 – EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it...

A Visit to SUSS MicroTec

It’s been a few years since I toured the US headquarters of SUSS MicroTec in Waterbury VT, so when general manager, Wilfried Bair invited me out to see their latest toolset developed...