Search Results

Matches for your search: "fan-out wafer level packaging "

ACM Research Adds Metal Lift Off Capability to Ultra C pr Tool to Support Power Semiconductor Manufacturing and Wafer Level Packaging Applications

First system qualified at power semiconductor manufacturer in China FREMONT, Calif., Nov. 11, 2022 (GLOBE NEWSWIRE) — ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) applications, today announced that it has expanded its Ultra C pr product offering to include...

IFTLE 537: 2022 IMAPS Society Awards Go to Advanced Packaging Superstars

IMAPS held its 55th International Symposium on Microelectronics in Boston, October 4-6 2022. The conference drew some 900+ attendees hungry for some post-pandemic social contact. It was somewhat of a homecoming for me since my career started in the Boston suburbs where I worked for 12 years (1975 – 1986) at Dow...

The Memory Packaging Market Shows Steady Growth

The memory industry is experiencing a strong growth phase: the total memory market is expected to increase at a ~9% CAGR 2016-2022, reaching about US$135 billion by 2022, with DRAM and NAND constituting almost 95% market share. Moreover, a supply-demand mismatch is pushing memory device asking selling price (ASP), resulting...

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

Multichip module (MCM),  system-in-package (SiP), system-on-chip (SoC), and heterogeneous integration are all important semiconductor packaging technologies. They deserve to have, at the very least, a book written about them. However, herein I would like to give these technologies very simple descriptions. if you don’t mind. MCM MCM integrates different chips and...

What’s New for the 2017 European 3D Summit

For the fifth consecutive year, the European 3D Summit returns to Grenoble, January 23-25, 2017. The event has evolved over those years, beginning its tenure as the 3D TSV Summit, then last year re-branded as the 3D Summit in acknowledgment that not everything in 3D has to do with through...

iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform

Each year, Apple integrates more and more innovative technologies in its iPhone products. This year, with the new iPhone 7 and its A10 processor, the leading company is the first organization to bring out package-on-package (PoP) wafer-level packaging (WLP) at the consumer scale. Apple underwent a strategic change by selecting...

Convergence on the “Big Five”: Focus on WLCSP

Part two of a five-part series. How did we determine which technologies are “the Big Five,” for semiconductor packaging? Essentially, we identified the five key platforms that we believe will be leveraged across a multitude of applications and markets now and in the future. The selected platforms are low-cost flip chip,...

At 3D ASIP 2015, Variety is the Spice of Life

Staying relevant in the ever-expanding technology landscape that is the semiconductor packaging industry can be a struggle for an event that’s been laser-focused on one emerging segment since its inception. But this past week, 3D Architectures for Semiconductor Integration and Packaging  (3D ASIP 2015) delivered a program that not only addressed...

Ideas for Co-optimizing Chip-Package Design

In a recent blog sharing my impressions of July’s Semicon West, I complained a bit about the lack of substantial IC packaging topics at this large IC manufacturing conference and also mentioned that I had observed the same problem at June’s Design Automation Conference. I am glad that I was fairly...

TechSearch International Analyzes Flip Chip and Wafer Level Package Growth

TechSearch International Analyzes Flip Chip and Wafer Level Package Growth Flip chip and wafer level package (WLPs) shipments continue to increase. TechSearch International’s new study, 2015 Flip Chip and WLP: Emerging Trends and Market Forecasts, provides unparalleled analysis of what’s behind the numbers for the growth of flip chip and...