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At last week’s International Microelectronics and Packaging Society’s Device Packaging Conference, (IMAPS DPC 2024) we didn’t need TrendForce to tell us that advanced packaging is the hottest technology in the semiconductor industry. We just needed to look at the record attendance of more than 700 advanced packaging enthusiasts who turned...
IMAPS 2022 Continued… This year’s IMAPS Symposium in Boston drew 925 attendees and featured: 20 technical and poster sessions 11 professional development courses Keynotes from MIT, Bosch, NXP, Reliance and ADI Panel session on mm wave packaging As always it was a great atmosphere to see old friends and make...
Malicious Embedded Chips in our Mother Boards? Early October brought a report from Bloomberg that I have heard was the top tech story circulating at the DoD and DARPA. For years, articles about counterfeit chips, and our reliance on Asian-made chips – where they could be modified in ways to pass...
MEPTEC lunches, now known as the MEPTEC / IMAPS / SEMI Semiconductor Speaker Series Luncheon sponsored by Chip Scale Review, are on again in Silicon Valley. At the most recent lunch in mid-March 2018, I was pleased to see that it was none other than Rich Rice, VP Business Development,...
Part 1 of my 3D ASIP blog covered the five keynotes presented at 3D ASIP 2017. Part 2 focuses on more than 20 informative presentations, where focused experts gave an in-depth view of new and/or improved technologies for 3DIC-related advanced packaging. Before we address these, allow me a one-sentence recap...
Sorry everybody, but I couldn’t resist this Buzzfeed-esque title, because Besi’s Hugo Pristauz’ unprecedented use of “colorful” language to illustrate the “turbulent plane ride” of ramping thermo-compression bonding die attach to volume production just might go down in history as the most talked (and laughed) about incident at the 2016...
Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a greater number of I/O contacts, at a lower cost. With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers, and power management ICs in...
I have to admit, after attending this week’s SEMICON West 2016, I’m feeling a little smug. Why? Because after years of waiting in the shadows for its day in the sun, advanced packaging is finally getting its turn, thanks to the push towards heterogeneous integration, which relies on advanced packaging...
Flanders, New Jersey (September 1, 2015) — Rudolph Technologies, Inc. (NYSE: RTEC) announced the widespread adoption and success of its newest macro defect inspection tool, the NSX®330 Series. The NSX 330 Series provides high-speed macro defect inspection and 2D and 3D metrology for advanced packaging applications, which are being developed to...
New NSX Metrology Series includes application-specific configurations to address unique metrology requirements for wafer level packaging, 2.5D and 3DIC Rudolph Technologies, Inc. (NASDAQ: RTEC), a leading provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its...
