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IMAPS 2022 Continued… This year’s IMAPS Symposium in Boston drew 925 attendees and featured: 20 technical and poster sessions 11 professional development courses Keynotes from MIT, Bosch, NXP, Reliance and ADI Panel session on mm wave packaging As always it was a great atmosphere to see old friends and make...
The annual IEEE Electronics Packaging Technology Conference (EPTC 2020 – Asia’s equivalent to the ECTC) took place virtually in December, instead of in Singapore as originally planned. With most of the world’s packaging being done in Asia, it is always a great source of interesting advanced packaging presentations. Let’s take...
With each passing year, emerging growth application areas such as Automotive, Cloud Computing, Industrial Automation, and Telecom (5G) Infrastructure are garnering more attention. Although the application segments are different, there is a commonality in how voltage conversion and power distribution are achieved at the system level. System demands are becoming...
In a recent IMAPS webinar, John Park (Figure 1), product management director of Cadence Design Systems, gave a tutorial entitled “This Is Not Your Father’s Advanced Semiconductor Packaging…an EDA Perspective”. Herb Reiter reviewed it here. While a lot of the technical detail that he shared was probably beyond the older...
The semiconductor industry is at a turning point. The slowdown in CMOS scaling, coupled with escalating costs, has prompted the industry to rely on integrated circuit (IC) packaging to extend the benefits of the More-than-Moore era. Thus, the advanced packaging industry has entered its most successful period, boosted by widespread...
EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the new SmartView® NT3 aligner, which is available on the company’s industry benchmark GEMINI® FB XT integrated fusion bonding system for high-volume manufacturing (HVM) applications. Developed specifically for fusion...
MEPTEC lunches, now known as the MEPTEC / IMAPS / SEMI Semiconductor Speaker Series Luncheon sponsored by Chip Scale Review, are on again in Silicon Valley. At the most recent lunch in mid-March 2018, I was pleased to see that it was none other than Rich Rice, VP Business Development,...
Sitting in the bus on the way back from Grenoble to Airport Lyon, I am reflecting the last two days during which we honored Gilles Poupon, the Advanced Packaging “Pope” of CEA Leti. Upon his retirement at the end of November 2017, somehow an era ends. I have known Gilles...
Sorry everybody, but I couldn’t resist this Buzzfeed-esque title, because Besi’s Hugo Pristauz’ unprecedented use of “colorful” language to illustrate the “turbulent plane ride” of ramping thermo-compression bonding die attach to volume production just might go down in history as the most talked (and laughed) about incident at the 2016...
Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a greater number of I/O contacts, at a lower cost. With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers, and power management ICs in...
