Search Results

Matches for your search: "fan-out wafer level packaging "

Will 3D Heterogeneous System Integration Help Scale the ESG Wall?

At SEMICON Europa 2023, we heard more good news about 3D heterogeneous Integration from speakers at the CEO Summit and the Advanced Packaging Conference. Not only has it become the champion for the continuation of Moore’s Law scaling, but it also allows us to deliver on power performance area and...

IMAPS Keynotes Focus on Heterogeneous Integration for HPC, AI, and EVs

This year’s IMAPS keynotes focused on advancements in heterogeneous integration (HI) technologies and chiplet architectures enabled by HI, driven by the needs of high-performance computing, AI, and automotive applications. While it feels for some of us that we’ve been in the thick of advanced packaging, HI, and the More than...

Autonomous Vehicles Drive AI Advances for Edge Computing

Advances in Edge Computing Must Innovate for Autonomous Vehicles to Realize Their Potential Large numbers of sensors, massive amounts of data, ever-increasing computing power, real-time operation, and security concerns required for autonomous vehicles are driving the core of computation from the cloud to the edge of the network. Autonomous vehicles...

Intel@14nm+@Skylake@Kabylake-S(DualCore)@Celeron_G3930@SR35K______DSC02678

System-on-Chip Disintegration is Underway

We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...

SEMICON West Keynotes Look to a Future Beyond Moore’s Law

In addition to Francoise’s post about technology megatrends here, below is part one of my perspective, mostly about the SEMICON West keynotes. Design and Manufacturing Are Finally Combining From July 9-11, many IC manufacturing experts came together at SEMICON West in San Francisco’s very nicely renovated Moscone Center. As an industry...

ISS 2019 Continued: Facing New Challenges and Opportunities

Just in case you didn’t have a chance yet to read part 1 of the ISS 2019 blog, covering day 1, it’s posted here. Technology and Manufacturing Trends Day 2 started with a keynote about the magic nanodevices can create, delivered byJo de Boeck, imec’s EVP and chief strategy officer. He emphasized that...

SEMI Alliance

Strategic Partnership with ESD Alliance Extends SEMI’s Reach to Semiconductor Design

On Monday, April 16, 2018, SEMI, the industry association representing the global electronics manufacturing supply chain, and the Electronic System Design (ESD) Alliance, representing the design community, announced a strategic partnership. On Tuesday I had a very informative conference call with Bettina Weiss, VP Business Development at SEMI and Bob...

IWLPC 3D Thursday: The Panel

It’s been a whirlwind of conferences these past few weeks, and as a result, I have attended FOUR panel discussions on 2.5D and 3D related topics. (I already wrote about the 3D Test Workshop Panel – 3D Buzz Hype or Reality. It’s stirred quite a discussion.) The day before I...

Altatech Semiconductor’s 300 mm CVD System Being Used in 3D IC Pilot Production at ASSID

All Silicon System Integration Dresden (ASSID), a leading-edge microelectronic wafer-level packaging and system integration center operated by the Fraunhofer IZM Institute, has begun pilot-line production of 3D semiconductor devices using a single-wafer, multi-chamber AltaCVD 300 system from Altatech Semiconductor S.A. At Fraunhofer IZM-ASSID’s 970-square-meter cleanroom facility in Dresden, Altatech’s

Following the BrightSpots 3D IC Forum

Day One: I'm not sure if it’s because it was the Monday after a U.S. holiday weekend, or just a Monday, but things seemed a bit slow out of the gate. I posted the first questions and waited. Paul Lindner of EV Group jumped right in on a positive...