Search Results

Matches for your search: "fan-out wafer level packaging "

SEMI Attends COP 27

SEMI Attends COP 27

COP 27 was held in the second and third week of November 2022. In the media, there was news of calls to accountability for promises made at COP 26, for which richer nations are still lagging. These included a $100 billion fund to assist smaller countries that are significantly impacted...

SEMI ISS 2022: Semiconductors Leading a Transforming World – Day 1 Highlights

  HALF MOON BAY, Calif. — April 5, 2022 — SEMI Industry Strategy Symposium (ISS) 2022 opened yesterday with the theme Semiconductors Leading a Transforming World to highlight semiconductor industry growth opportunities and challenges. The annual three-day conference of C-level and senior industry executives gives a comprehensive outlook of global electronics...

How Are Logic and Memory Makers Addressing Sustainability?

Addressing sustainability issues is a hot topic in the semiconductor industry, especially since Bloomberg highlighted that the industry’s carbon footprint is growing at a rapid clip while the auto industry’s carbon footprint has declined over the same period. However, the article only calls out GM as the automaker of reference....

ESD Alliance Webinar about Export Compliance with Insights from an Expert

In the ESD Alliance line-up of Fall 2021 events, next is a webinar on export compliance, a topic that affects all companies in the 3D InCites community and semiconductor industry, not just the system design ecosystem as the title implies. The “Understanding Export Regulations Affecting the Electronic System Design Ecosystem”...

Why We Need to Address Known Good Die (KDG) Holistically

If you love, like me, to work on the bleeding edge of technology, you will find that your personal success depends very much on the team around you, your company, even the entire supply chain. The organizers of this workshop – AMD’s Michael Alonso, Advantest’s Dave Armstrong, and MEPTEC’s Ira...

DAC 2016: There is More to Life than IC Design

In the past, the Design Automation Conference was known to me and many of my colleagues as the annual event that focused on IC design tools, flows, and methodologies. EDA tools vendors and users got together in the previous millennium to discuss what to do next in a rapidly growing market...

DesignCon 2015: Blasting Through Walls with Holistic Planning

DesignCon’s 2015‘s tag-line “where the chip meets the board”, was a very appropriate message, and summarized in a few words a major trend in our semiconductor- and electronic systems industry: The increasing need for holistic planning as well as modeling of building blocks, not only for better up- and down-stream...

Are Chip Architects Finally Climbing on the 2.5D and 3D Bandwagon?

Ever since SEMICON West 2014, I’ve been seeing a lot of coverage of the 2.5D and 3D adoption question on Semiconductor Engineering, an industry content platform that covers the spectrum of semiconductor topics, and occasionally covers 2.5D and 3D, providing the perspective of chip architects, engineers, end users, industry organizations...

Are there still Gaps in 3D IC Readiness?

Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words I’ve been waiting to hear her say for quite some time. “Memory stacks with TSVs are here!” Vardaman cited three companies actively involved in new memory architectures, all of which...

Courtesy of Apple and IBM

Apple and IBM on the Way to Demonstrate That ONE plus ONE is More Than TWO

Tuesday’s (July 15) Nightly Business Report surprised me with an – in my view – very important announcement: Apple and IBM are going to cooperate to offer enterprise solutions. See more about this significant step here and in many other headline news coming out this week. The former rivals are...