Search Results

Matches for your search: "fan-out wafer level packaging "

February member highlights

February Member Highlights – Acquisitions, Awards, Events, New Offerings and More

The 3D InCites community members continue to create a buzz with announcements from new acquisitions to industry awards, new product introductions, events, job openings, and more. Here’s a collection of February member highlights. Acquisitions, Partnerships and Collaborations ASE announced a strategic partnership with Infineon Technologies, to acquire two back-end manufacturing...

Update on the UCIe™ from ITC 2022

In 1965 Gordon Moore proclaimed that there would be a “’Day of Reckoning’ when it may prove to be more economical to build large systems out of smaller functions…”.  The 2022 IEEE International Test Conference, held live and in-person for the first time since the pandemic, addressed the implications of...

Francoise von Trapp to Speak on Heterogeneous Integration at MicroTech 2021

Francoise will be presenting A Sustainable Future Requires Heterogeneous Integration at MicroTech 2021, the Annual IMAPS-UK Conference. Session 5 at 3:15pm Abstract: In September 2015, 193 member states of the UN adopted 17 new sustainable development goals (SDGs) to make our world more prosperous, inclusive, sustainable, and resilient. As a...

Intel Fellow Wilfred Gomes, a member of Intel’s Silicon Engineering Group, holds a processor with the advanced packaging technology called Foveros. It combines unique three-dimensional stacking with a hybrid computing architecture that mixes and matches multiple types of cores for different functions. (Credit: Walden Kirsch/Intel Corporation)

Chiplets: The New Era Begins

The semiconductor industry has entered a new era and the role of design including the package has become increasingly important. No longer can the industry count on monolithic integration to achieve the economic gains of the previous era. New packaging solutions are being adopted to achieve the economic advantages that...

Talking about Technology Megatrends at SEMICON West 2019

What a difference a year makes. First the aesthetic: after two years of maneuvering around a construction zone at SEMICON West, the Moscone Center renovation is complete and looks fabulous. It’s also so much easier to navigate between halls, and to and from the keynote stage at the newly christened...

3D IC Business Model: A Customer Decision

After more than a year of touting the turnkey model, even TSMC is jumping on board the collaboration bandwagon for manufacturing 2.5D and 3D ICs at high volume. This revelation came this week at ECTC 2013 (May 28-31, Las Vegas) from TSMC’s Jerry Tzou, who was a panelist during the...

“Known Good Die” has a new name

After 20 years of chasing elusive Known Good Die (KGD) to achieve high yielding advanced interconnect technologies, the semiconductor industry has come to the conclusion that its time to take a different approach. It’s called Probably Good Die, and when it comes to 2.5D and 3D ICs, particularly for Memory,...

Update on 3D transistors (That “other” 3D)

I always hesitate to cove 3D transistors, because before they came along, I only focused on what I knew to be 3D – ie: 3D stacked packages, 2.5D interposers and 3D ICs. And that was confusing enough. But then along came Intel’s Tri-Gate technology, claiming the 3D moniker as its...

Simulation and Modeling Tools enable 3D MEMS Systems

One of the main themes of last week’s MEMS Executive Congress was to “think outside the chip” (Roger Grace, of Roger Grace Associates) and rather, think of MEMS in terms of the system.  However, to do that, there needs to be interaction between everyone involved in developing said system, including...