Matches for your search: "fan-out wafer level packaging "
Don’t let the skeptics fool you, contrary to popular belief, the 3D test community has been hard at work on solutions for overcoming 3D test challenges. I am attending The Fourth IEEE International Workshop on testing 3D Stacked ICs (3D Test Workshop for short) at the Disneyland Hotel in Anaheim,...
Naysayers be damned! Full commercialization for 3D ICs in smartphones may be a few years out, but that doesn’t dampen the spirits of the truly devoted, who latch on to every forward step as a monumental accomplishment. This week, progress appears to be taking off for 2.5D products, and the...
Has it really been a month since the European 3D TSV Summit? This inaugural event certainly caused a buzz in the blogosphere! In addition to all my coverage after having attended the event, Phil Garrou has been slogging his way thorough the proceedings to provide an in-depth review on Insights...
After attending last week’s 9th Annual Architectures for Semiconductor Integration and Packaging Conference in Redwood City, CA, it’s pretty clear that there’s probably the same chance of 3DIC NOT happening, as there is a chance the world will end on Dec 21. (And oh by the way, Tom Pawlowski, chief...
The latest digital issues of Chip Scale Review and iMicronews’ 3D Packaging magazines hit the virtual “stands” last week, and perhaps in honor if the 3D ASIP Conference that gets underway later this week, there are some hot new 3D technologies being featured. But first, to bring everyone up to...
Glass interposers got a thumbs up from i-MicroNews in a “Closer Look” post reviewing Corning’s Peter Bocko’s presentation at IMAPS 2012. Based on work done as part of Ga Tech’s consortium, Bocko demonstrated that “glass interposers show less warp during chip assembly, faster signal propagation and significantly reduced signal loss. In...
Georgia Tech’s Packaging Research Center, in its pioneering chip-last embedded interconnection technology, demonstrates World's Thinnest 3D Organic Package at 130um thickness at 30um interconnection pitch using ultra-short copper-copper interconnections and bonding below 200oC for highest electrical performance. The "Ultra-SLIM Packages have built-in vertical connections to the top surface
The Burn‐in & Test Socket Workshop (BiTS Workshop) announced today that it is changing its name to The Burn‐in & Test Strategies Workshop (BiTS Workshop). The rebrand, which features an updated logo, is reflected in all of BiTS collateral material and the website for the 2012 BiTS Workshop that takes...
Two weeks ago, wearing my Chip Scale Review Sr. technical editor hat, I attended (along with 11 other journalists) an exclusive press conference launching a new electronic interconnect company, Deca Technologies, which claims to have developed disruptive manufacturing processes based on its sister company, SunPower’s, solar cell wafer processes, rather...
SEMICON Singapore gets underway next week (May 19-21), and the 3D track speaker line-up features presentations by several 3D InCites partners. If you plan on attending, be sure to put these sure-to-be interesting talks on your personal agenda.
