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The semiconductor industry has made great strides in ASIC technology over the last 40 years, leading to better performance. But as Moore’s law nears its limits, scaling devices is becoming harder. Shrinking devices now takes longer, costs more, and presents challenges in technology, design, analysis, and manufacturing. Developers of high-end...
The semiconductor industry’s decades-long adherence to Moore’s Law doctrine of doubling transistor counts on monolithic devices every 18 – 24 months has been amazingly successful. It’s now possible to integrate tens of billions of transistors onto a monolithic die whose area may be hundreds of square millimeters. The resulting chips...
The 4th CIIE was held successfully, let’s see which semiconductor companies appeared at the event. The opening ceremony of the 4th China International Import Expo (CIIE) and Hongqiao International Economic Forum was held in Shanghai on November 4th, 2021. Nearly 3000 exhibitors from 127 countries and regions appeared, and the...
EVATEC AG, a leading supplier of thin film equipment and process solutions in Advanced Packaging, Semiconductor, Optoelectronics and Photonics applications, has successfully completed the installation of a Clusterline 600 Panel Level Packaging Etch system at Fraunhofer IZM, Berlin. The CLN600 platform is a dedicated Etch and Sputter equipment for FO-PLP...
Technology innovations don’t reach customers right away. Since 1980 I have observed how our industry has improved key parameters like cost per function, power dissipation, form-factor, complexity and clock-speed by many orders of magnitude. However, every new technology took at least several years, sometimes more than a decade, until it...
I am fortunate to work with Prof. Madhavan Swaminathan, Founder, CTO, E-System Design, and inventor of our algorithms. Long ago, as an undergraduate engineering student at University of Illinois focused on integrated circuit (IC) design, I enrolled in the required ElectroMagnetics (EM) course to discover it was all about large...
I almost didn’t attend the keynote panel titled, Scaling the Walls of Sub 14nm Manufacturing, at SEMICON West last week, because in my experience as a blogger/journalist focused on advanced packaging, interposer integration and 3D ICs, discussions on scaling rarely talk about packaging. In fact, up until now, it’s been...
Stacking transistors on top of each other sequentially in the same front-end process flow is a concept that has been imagined to provide the semiconductor community with an alternative to the traditional scaling paradigm challenged by technical and cost roadblocks. LETI Advanced CMOS Laboratory introduced CoolCube™, a low-temperature process flow that provides...
The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of...
2.5D Interposer: A configuration where dies are mounted side by side on one side of a thin (~ 100 um) silicon, glass, or organic interposer using through silicon vias (TSVs), through glass vias (TGV) or through substrate vias (TSV), respectively through the interposer to connect the dies with the package...
