Matches for your search: "fan-out wafer level packaging "
EVATEC AG, a leading supplier of thin film equipment and process solutions in Advanced Packaging, Semiconductor, Optoelectronics and Photonics applications, has successfully completed the installation of a Clusterline 600 Panel Level Packaging Etch system at Fraunhofer IZM, Berlin. The CLN600 platform is a dedicated Etch and Sputter equipment for FO-PLP...
San Jose, California – USA – The International Wafer-Level Packaging Conference and Expo announces Dan Oh, Ph.D., Engineering VP of the Test & System Package (TSP) unit at Samsung Electronics will deliver the opening keynote presentation of the virtual event. The presentation, “Trends, Challenges, Opportunities in Advanced Packaging for Smart...
Technology innovations don’t reach customers right away. Since 1980 I have observed how our industry has improved key parameters like cost per function, power dissipation, form-factor, complexity and clock-speed by many orders of magnitude. However, every new technology took at least several years, sometimes more than a decade, until it...
SEMI held its annual Industry Strategy Symposium (ISS 2019) at the Ritz Carlton in Halfmoon Bay, CA January 6-9, 2019. Many high-level executives represented key areas of the electronic products supply chain. Former government officials emphasized that our country’s leaders recognize the strategic importance of semiconductors. The theme of ISS...
Stacking transistors on top of each other sequentially in the same front-end process flow is a concept that has been imagined to provide the semiconductor community with an alternative to the traditional scaling paradigm challenged by technical and cost roadblocks. LETI Advanced CMOS Laboratory introduced CoolCube™, a low-temperature process flow that provides...
The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of...
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool...
Wouldn’t it be great to get a text notification that you are almost out of toilet paper at home rather than when it’s well… almost too late? Or how about an intra-nasal sensor that detects the level of acetone in your breath to tell you if you’re accumulating or burning...
When is an active die not an active die? When it’s an active interposer, of course! Ever since Nicolas Sillon, former head of CEA Leti’s 3D Integration program, first talked about the research institutes’ work with interposer technology for 3D integration, the term “active interposer” has sparked controversy and begged for definition....
2.5D Interposer: A configuration where dies are mounted side by side on one side of a thin (~ 100 um) silicon, glass, or organic interposer using through silicon vias (TSVs), through glass vias (TGV) or through substrate vias (TSV), respectively through the interposer to connect the dies with the package...
