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Live from “Silicon Desert”: The news is all about huge spending by TSMC and Intel. Investment in advanced packaging (2.3/2.5/3D including chiplets) is increasing. As a 5nm design effort tops $500M and photo tools approach $150M, it was necessary to bust up systems-on-chip (SoCs) into re-partitioned systems – where functions...
A recent Wall Street Journal article, The Microchip Era Is Giving Way to the Megachip Age, explains how the chip industry is transitioning from monolithically integrated chips to stacking chiplets to make megachips. In the U.S., DARPA is embarking on the Next Generation Microelectronic Manufacturing initiative focused on three-dimensional heterogeneous...
Reno Sub-Systems (Reno), a developer of high performance radio frequency (RF) matching networks for leading-edge nanoscale semiconductor manufacturing, today introduced its new GenMatch™ Series that integrates the company’s proven solid-state Electronic Variable Capacitor (EVC™) RF match and Precis™ generator technologies into a single unit. The systems have a footprint similar...
In order to remain competitive in the Internet-of-Things (IoT) environment, medium-sized industrial and process measurement technology companies must increasingly integrate their sensor circuits on ASICs (Application Specific Integrated Circuits). The semiconductor industry is currently meeting this need with lower costs for development processes and lower thresholds in terms of production...
Eight years in the making, the IEEE Std 1838™-2019 Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits — or IEEE 1838, DfT for 3D IC, as it’s known in inner circles – was published on March 13, 2020. Simply put, this standard will allow stacked dies in 3D ICs to connect...
There’s probably no more fitting venue for discussing future directions for processing and packaging technology in integrated circuit fabrication than the Computer History Museum in Mountain View, CA. After all, “The mission of the Computer History Museum is to preserve and present for posterity the artifacts and stories of the...
Semiconductor supply chain, ecosystem, value chain: whatever you call it, its become a hot topic of discussion, and one that is near and dear to my heart as a supporter of 3D IC commercialization. Well over a year (maybe even going on two) we’ve been hearing suggested changes like a...
While it was Good Friday for most, it was 3D Friday for those of us who attended the 19th Annual Electronic Design Process Symposium (EDPS), held last week in Monterey CA. What an amazing location! For an ocean-starved desert dweller like me, it was hard to tear my eyes off...
I just finished putting together a presentation for the upcoming BiTS Workshop March 7-10, 2010 taking place in my backyard in Mesa, AZ.
The SMTA and Chip Scale Review magazine are pleased to announce five half-day tutorials for the 6th Annual International Wafer-Level Packaging Conference, held October 27-30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, California.
The IWLPC tutorials are application oriented and structured to combine field experience with...
