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Indium Corporation Technical Expert to Present at SiP Conference China

Indium Corporation Senior Area Technical Manager for East China, Leo Hu, is scheduled to deliver a presentation on low-temperature solder material in semiconductor packaging applications at SiP China Conference 2024 on November 27 in Suzhou, China. The presentation, titled Low-Temperature Material Discovery and Readiness for First-Level Interconnect in Semiconductor Packaging, will explore the latest advancements...

Multi-Tier Die Stacking Enables Efficient Manufacturing

Achieve higher integration density with collective die-to-wafer bonding Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes...

May Member News

May Member News: Strategic Moves, Product Launches, Sustainability and more

May member news showcases significant strides in advancing semiconductor technologies and fostering sustainability efforts. From strategic divestitures and innovative product launches to educational initiatives and workforce development programs, the semiconductor industry continues to evolve and thrive. Dive into the latest updates from our member companies and stay informed about the...

Taiwan Semiconductor Research Institute Selects Veeco MOCVD System for Advanced R&D and Technology Collaboration for Power and RF Applications

Plainview, N.Y., June 8, 2022—Veeco Instruments Inc. (NASDAQ: VECO) today announced that the Taiwan Semiconductor Research Institute, National Applied Research Laboratories (TSRI, Narlabs) has selected Veeco’s Propel® R&D Metal Organic Chemical Vapor Deposition (MOCVD) System for advanced development and collaboration related to gallium nitride (GaN)-based power and RF devices.  The...

SemiSister Success Story: A Woman on the Edge of 3D Technology

Severine Cheramy has devoted her career to developing 3D integration technologies and bringing them to market. She was the first person to show me what a TSV wafer looked like when I visited CEA-Leti’s cleanroom in 2009 during my Tour de France in 3D. At the time, she was a...

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3D IC Test: Now and The Road Ahead

Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing...

SEMATECH: hitting 3D head-on

At last week’s SEMATECH technology round-up webcast, Sitaram Arkalgud, director of 3D interconnect, made a comment about 3D technologies that, in my opinion, really brought all the issues swirling around it to one vital point. It was this: as a platform, 3D allows a whole other scheme of processes to...

EVG’s partnership with Léti adds a third dimension

As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti...

TSVs: just the tip of the 3D ICeberg

At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle...

The post-fab process debate for 3D ICs: foundry or OSATS

Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way...