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Meet Trymax’ most flexible Plasma Ashing system for running critical low-temperature descum processes and high-temperature bulk photoresist strip processes. These steps are crucial for the manufacturing of high-performance accelerometers and gyroscopes used in consumer, automotive and industrial applications. Our NEO 2000 system prepared for MEMS manufacturing is the latest photoresist...
Severine Cheramy has devoted her career to developing 3D integration technologies and bringing them to market. She was the first person to show me what a TSV wafer looked like when I visited CEA-Leti’s cleanroom in 2009 during my Tour de France in 3D. At the time, she was a...
Wilmington, Mass. (November 1, 2018)—Rudolph Technologies, Inc. (NYSE: RTEC) today announced the availability of its NovusEdge™ system for edge, notch and backside inspection of unpatterned wafers. The company plans to ship multiple systems totaling more than $3M by year end to fill existing orders from two customers. The new system is...
Continuing from Part 1: On Thursday morning I really enjoyed the Monolithic 3D session. Francoise already reported about it, so I can be brief and focus on the most advanced program presented, the CEA Leti CoolCube™ . Olivier Billoint showed and explained how Leti, in cooperation with an EDA partner, is...
Another early start (5:30am) to catch the train to Grenoble. The trains went on strike (a regularly scheduled occurrence) but lucky for me, the strike didn’t affect trains running before 8am. (I love France. They’re so civilized here…) As I wasn’t scheduled to meet with the team from Soitec until...
It’s hard to believe I’ve been at this for a almost a year.
As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti...
SUSS MicroTec and IMEC have entered a joint development program to develop permanent bonding, temporary bonding and debonding processes for 3D system integration, including through-silicon-via (TSV) manufacturing.
At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle...
Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way...
