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Commercial Times reports that TSMC’s Arizona wafer fab, Fab 21 Phase 1, has officially entered mass production on its 4nm process. Monthly capacity is expected to reach 30,000 wafers by mid-year. Construction of Fab 21 Phase 2 and Phase 3 are set to proceed this year and next, with fab...
The dedicated HVM EVG®880 LayerRelease™ system boosts productivity and lowers the cost-of-ownership of novel infrared laser release technology through silicon carrier wafers for 3D integration applications EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology, and semiconductor markets, today introduced the EVG®880 LayerRelease™...
Hello, I am Mandy Perdok. I am 20 years old and live in Milsbeek in the Netherlands. My hobbies include playing Netball (Team Sport), training/coaching the Netball youth team, and traveling. As a third-year student majoring in Chemical Engineering at the Fontys Hogeschool Eindhoven of Applied Science, I am completing...
Artificial intelligence and machine learning (AI/ML) can have various applications in smart manufacturing for semiconductor fab, advanced packaging, and electronics manufacturing, and it typically involves several key elements: sensing, connectivity, predicting, and control. As recognized by many industry organizations, smart manufacturing matures through several levels: reactive, preventive, predictive, and autonomous...
PROPHESEE Joins IRT Nanoelec 3D Integration Program Will Work with CEA-Leti, STMicroelectronics, Mentor, EVG, and SET to Develop New 3D Event-Based Vision System GRENOBLE, France – Oct. 14, 2019 – PROPHESEE, the inventor of the world’s most advanced neuromorphic vision systems, joins the IRT Nanoelec consortium to help broaden the...
Who was Madeline on Halloween? Before we start more tech coverage of IMAPS 2018 with a look at polymer dielectric advancements, long time readers know that you are due a Halloween update on my granddaughters. This year I’m focusing on Madeline who will be eleven in February. Her Halloween disguise...
Wafer and panel-level packaging (WLP/PLP) offers technical and business advantages, compared to traditional IC packages. These cost-effective packaging solutions attracted more than 800 industry experts to the International Wafer Level Packaging Conference (IWLPC 2018) in San Jose’s DoubleTree Hotel at the end of October. In case you were wondering, a...
Last week, September 13 to be exact, TSMC held its Open Innovation Forum (OIP 2017) Symposium at the Santa Clara Convention Center. Before getting into product and market details, allow me to share some of my general impression of this, as usual, very well-organized event. After several decades of experience...
A few weeks ago, Tezzaron announced its latest industry first: an eight-layer 3D IC wafer stack containing active logic, built at its fab, Novati Technologies, a global nanotechnology development center located in Austin, TX. Novati is clearly on a roll, because today they added another industry first to their product...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
