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Indium Corporation Senior Area Technical Manager for East China, Leo Hu, is scheduled to deliver a presentation on low-temperature solder material in semiconductor packaging applications at SiP China Conference 2024 on November 27 in Suzhou, China. The presentation, titled Low-Temperature Material Discovery and Readiness for First-Level Interconnect in Semiconductor Packaging, will explore the latest advancements...
Achieve higher integration density with collective die-to-wafer bonding Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes...
While most of us in advanced packaging is familiar with CEA-Leti, CEA-List ( Laboratoire d’Intégration de Systèmes et des technologies) is one of three specialized technological research institutes of CEA specializing in digital systems. Denis Dutoit, of CEA-List, presentation on “Chiplet Partitioning Can Balance Among Performance, Flexibility and Scalability” at...
SUSS MicroTec, leading supplier of equipment and process solutions for the semiconductor industry, announced today a far-reaching collaboration agreement with BRIDG, a not-for-profit, public-private partnership focused on production process technologies, advanced system integration, and 200mm microelectronics fabrication advancing next-generation nanoscale technology. This partnership puts an unprecedented array of SUSS MicroTec...
The Electronic Design Process Symposium – EDPS 2919 – is known in the IC design community as a rather small (50 – 100 participants), but a highly interactive workshop. The 26th edition, hosted again this year by SEMI at its Milpitas headquarters, October 3 -4, 2109 featured both EDPS IC design...
From the keynotes to the sessions to casual conversation, automotive electronics was a hot topic of discussion at SEMICON Europa 2017. That’s likely because Europe leads the world in automotive OEMs and is home to four of the top 10 semiconductor providers in the automotive industry. With over 22% growth...
Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing...
Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family of 3D integration technology possibilities, we’ve been careful to define them separately on 3D InCites. Some people have wondered if one will displace the other, or if these technologies would...
When I saw that Dev Gupta, Ph.D, of Advanced Packaging & Systems Technology Laboratories, LLC (APSTL) was presenting at the IMAPS Arizona Chapter luncheon last week, there was no questioning my attendance. Dr. Gupta has been an active participant on 3D InCites, offering regular commentary on posts, so I was...
At last week’s SEMATECH technology round-up webcast, Sitaram Arkalgud, director of 3D interconnect, made a comment about 3D technologies that, in my opinion, really brought all the issues swirling around it to one vital point. It was this: as a platform, 3D allows a whole other scheme of processes to...
