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IFTLE 621: TSMC Chip and Package Activity in the U.S.

Commercial Times reports that TSMC’s Arizona wafer fab, Fab 21 Phase 1, has officially entered mass production on its 4nm process. Monthly capacity is expected to reach 30,000 wafers by mid-year. Construction of Fab 21 Phase 2 and Phase 3 are set to proceed this year and next, with fab...

Adeia Wins ECTC Award for Paper on “Fine Pitch Die-to-Wafer Hybrid Bonding”

SAN JOSE, Calif.—July 10, 2024—Adeia Inc. (Nasdaq: ADEA), a leading research and development and intellectual property licensing company known for bringing innovations in the semiconductor and media technology sectors to market, was awarded Best Session Paper at the 2024 Electronic Components and Technology Conference (ECTC) held in Denver, Colorado on...

When Plasma Matters

As the company boasts some of the most advanced plasma equipment in the industry, CCO Peter Dijkstra discusses how Trymax Semiconductor Equipment B.V. (Trymax) has achieved this unique position. Amongst many titans of the semiconductor manufacturing industry in the Netherlands, Trymax Semiconductor Equipment B.V. (Trymax) is the company of choice...

Micross Components Acquires Semi Dice

Melville, NY (July 1, 2021) – Micross Components (“Micross”), a leading provider of high-reliability microelectronic product and service solutions for aerospace, defense, space, medical and industrial applications, today announced the acquisition of Semi Dice, LLC (“Semi Dice”), a global provider of high-reliability die & wafer products and value-added services. The...

PROPHESEE Joins IRT Nanoelec 3D Integration Program

PROPHESEE Joins IRT Nanoelec 3D Integration Program Will Work with CEA-Leti, STMicroelectronics, Mentor, EVG, and SET to Develop New 3D Event-Based Vision System GRENOBLE, France – Oct. 14, 2019 – PROPHESEE, the inventor of the world’s most advanced neuromorphic vision systems, joins the IRT Nanoelec consortium to help broaden the...

The Cost of 3D ICs

When 3D integration has been discussed in the past, whether in terms of a true 3D IC stack or an interposer-based design, the cost of 3D ICs has not always been part of the discussion. In the past couple of years, as 3D ICs have moved closer to reality, more attention...

Having the Courage to Design in 3D TSVs

I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I think Ron Huemoeller, Amkor, finally hit on it in his closing remarks during today’s webcast, “TSV Packaging at the Tipping Point”, moderated by Pete Singer, Solid StateTechnology/Extension Media. Huemoeller’s presentation and...

3D TSV Test Approaches: Outlook for 2014

Metrology, process control, and electrical test are key enablers for the success of the semiconductor industry. 3D integration using TSVs offers new challenges in this area that need solutions. There seems to be industry consensus that it is extremely difficult to perform a wafer-level test that ensures the complete functionality of...

EV Group Unveils New Via-Filling Process to Improve Reliability of 3D-IC / TSV Packaging

Semicon Taiwan, Taipei, September 4, 2013 — EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled a new polymer via-filling process for 3D-IC/through-silicon-via (TSV) semiconductor packaging applications.  Available on the EVG100 series of resist processing systems, the new...