Search Results

Matches for your search: "fan-out wafer level packaging "

SUSS MicroTec and BRIDG to Establish a Production-Level Applications Center in North America

Dec 03, 2019

SUSS MicroTec, leading supplier of equipment and process solutions for the semiconductor industry, announced today a far-reaching collaboration agreement with BRIDG, a not-for-profit, public-private partnership focused on production process technologies, advanced system integration, and 200mm microelectronics fabrication advancing next-generation nanoscale technology. This partnership puts an unprecedented array of SUSS MicroTec...

3D IC Test: Now and The Road Ahead

Apr 04, 2016

Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing...

DATE 2015 demonstrates Europe’s commitment to Semiconductors, Part 2

Mar 26, 2015

Continuing from Part 1: On Thursday morning I really enjoyed the Monolithic 3D session. Francoise already reported about it, so I can be brief and focus on the most advanced program presented, the CEA Leti CoolCube™ . Olivier Billoint showed and explained how Leti, in cooperation with an EDA partner, is...

Xilinx Ultrascale+: 3D on Steroids

Feb 26, 2015

Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family of 3D integration technology possibilities, we’ve been careful to define them separately on 3D InCites. Some people have wondered if one will displace the other, or if these technologies would...

Tour de France in 3D – Day 2

Dec 12, 2012

Another early start (5:30am) to catch the train to Grenoble. The trains went on strike (a regularly scheduled occurrence) but lucky for me, the strike didn’t affect trains running before 8am. (I love France. They’re so civilized here…) As I wasn’t scheduled to meet with the team from Soitec until...

SEMATECH: hitting 3D head-on

Dec 12, 2012

At last week’s SEMATECH technology round-up webcast, Sitaram Arkalgud, director of 3D interconnect, made a comment about 3D technologies that, in my opinion, really brought all the issues swirling around it to one vital point. It was this: as a platform, 3D allows a whole other scheme of processes to...

2009 Reflections in 3D

Dec 29, 2009

It’s hard to believe I’ve been at this for a almost a year.

EVG’s partnership with Léti adds a third dimension

Sep 04, 2009

As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti...

TSVs: just the tip of the 3D ICeberg

Jun 06, 2009

At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle...

The post-fab process debate for 3D ICs: foundry or OSATS

Apr 29, 2009

Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way...