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Net Zero

Getting Every Semiconductor Company to Net Zero

My sustainability news feed has been filled with articles regarding COP 28, and news of successes and failures regarding the reduction of CO2 levels in 2023. Most of these are focused on the prospect of missing the 1.5°C target set in Paris, the positives and negatives of carbon capture, the...

3D InCites Community Member Monthly Highlights — June

Our 3D InCites Community Members had an abundant amount of news to share this month, so we thought we should do a quick recap in our June edition of monthly highlights. If you have news to share, please don’t forget to share it with your 3D InCites team! ASE announced...

Plasma-Therm Receives Follow-on Order for HeatPulse RTP System for SiC Power Devices

Innovative platform redesign enables device makers to make critical system upgrades for currently installed legacy systems without interrupting processes of record   Tokyo, Japan & SEMICON Japan, December 15, 2022 — Plasma-Therm, a leading manufacturer of plasma-process equipment for the semiconductor and compound semiconductor industries, today announced it has received...

Industry Outlook: What Goes Down Must Come Up

The GDP is down, the stock market is up, unemployment, at least in the USA, is confused, so what is the semiconductor and semiconductor equipment market going to look like in the second half of 2020? Second-half forecasts typically begin to emerge in early July shortly before or during Semicon...

At the Crossroads of CVD and ALD, KOBUS Makes its Mark on 3D TSVs

Last July at SEMICON West, I was honored to witness the dramatic unveiling of UnitySC, the new company formed as a result of Fogale Group’s acquisition of Altatech, resulting in a semiconductor equipment portfolio that spans the spectrum of process control needs for advanced wafer-level and 3D packaging, including metrology,...

Fine Tuning Processes for TSV Reveal

Through silicon via (TSV) reveal is a critical part of the wafer-thinning step in 3D IC backside processing, where the wafer is thinned to expose the Cu “nails” that ultimately form the interconnect between die stacks. Some of the risks involved in this step include backside contamination (Cu diffusion) due...

Catching up with EV Group’s Dave Kirsch

Almost a year ago, Dave Kirsch took over the reins from Steve Dwyer as VP and General Manager of EV Group North America. Since EV Group launched a tool last week at SEMICON Singapore, and since EVG NA’s headquarters are practically in 3D InCites’ back yard, I thought it was...

Willkommen in Österreich!

Note to self: when visiting a class 10 clean room that requires full clean room attire (bonnet, booties, coverall, hood and boots) don’t wear a skirt!